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Open roles at AMD, page 23

  • Senior Firmware Developer in Hyderabad
  • RTL Design Engineer With high-speed interfaces Exp in Hyderabad
  • Principal Software Developer - GPU AI/HPC kernels in Austin
  • SOC / System Validation Architect in Bengaluru
  • Frontier AI Workloads - Performance and Scalability Engineer in San Jose
  • Senior RTL design engineer - SOC Intergration in Hyderabad
  • High-Speed SERDES Validation Engineer in San Jose
  • Staff Silicon Design Engineer - DTCO & PDK Development in Seoul
  • AI Framework Eng. in Shanghai
  • Program Manager in Singapore
  • Lead Embedded Linux kernel device driver development engineer in Bengaluru
  • RTL Synthesis and constraints Lead in Hyderabad
  • ASIC/SoC Design Engineer in San Jose
  • Staff DevOps Engineer - Compiler Infrastructure in Austin
  • Embedded SoC Architect in San Jose
  • Regional Employee Relations Manager in Singapore
  • Lead Memory Systems Design Engineer in Austin
  • Fellow, Server CPU / Post Silicon Architect in Santa Clara, Austin
  • Lead verification Engineer - high speed protocol in Hyderabad
  • Post-Training Platform Infrastructure Engineer in San Jose
  • Platform Architect – BIOS/Firmware & Customer Enablement in Bengaluru
  • Employee Relations Manager in Penang
  • Leadership Role - Emulation in Hyderabad
  • Sr. Director Data Center GPU Platform & System Validation GPU in Austin
  • Package Thermal Technologist in Austin
  • CVP, Data Center GPU Performance Architecture in Austin
  • HPC/AI Computational Scientist / Engineer - Center of Excellence in Paris
  • High Speed SR Signal and Power Integrity Engineer in Santa Clara
  • Lead Performance Engineer in Bengaluru
  • Linux Kernel SW Engineer in Austin
  • IP Verification Engineer in San Jose
  • Principal Software Engineer – PyTorch Training Frameworks in San Jose
  • Sr. Emulation Methodology Engineer in Austin
  • DFT Staff Engineer in Santa Clara
  • Post-Silicon Power and Performance Senior Staff Engineer in Penang
  • Senior Pre-silicon Validation Engineer - Emulation in Bengaluru
  • Principal Engineer, Physical AI in Markham
  • Senior Design Verification Engineer in Romania
  • CPU Formal Verification Engineer in Cambridge
  • RAS Lead in Bengaluru
  • SOC Silicon Design Engineer in United States
  • Pre‑Silicon Power Modeling Leader — x86 SoCs in Austin
  • System-On-Chip Failure Diagnostic and Debug Intern in Singapore
  • CVP of Applied AI FDE in San Jose
  • Silicon Photonics Validation and Characterization Test Engineer in San Jose
  • CPU Core Verification Engineer in Austin
  • CPU Core Design Verification Engineer in United States
  • Manager – Post silicon Validation in Bengaluru
  • Staff SerDes DSP RTL Engineer in United Kingdom
  • Test Development, Qualification, and Optimization for Next Generation AMD Server Products Intern in Singapore

Page 23 of 24, 1,170 open roles

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