RTL Design Engineer With high-speed interfaces Exp

Design and implement RTL for PCIe-based technologies (Gen6/Gen7) and high-speed interfaces (PCIe, CXL, NVMe, Ethernet) for programmable silicon at AMD. Collaborate across global teams from architecture through validation, develop testing plans, and contribute to IP design, silicon bring-up and IP release while applying Verilog/SystemVerilog, RTL simulators, and scripting to drive pre- and post-silicon validation in a datacenter-focused product line.