ASIC/SoC Design Engineer

AMD
San Jose
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Verilog","SystemVerilog","SVA","SDC","AMBA AXI","APB","UPF","Per l","Python","Makefile","Synthesis","STA","LINT","LEC","CDC","RDC"]

Seeking an ASIC/SoC design engineer to drive microarchitectural design and RTL implementation for Adaptive SoC and FPGA configuration systems. Collaborate across hardware, firmware, and software teams, and lead from concept to production silicon including timing analysis, DFT, and power/area optimization. Strong Verilog/SystemVerilog, SDC constraints, and AMBA protocols experience are required.

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FursaFursa
AMD
AMD
6 months ago

ASIC/SoC Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 12 hours agoStatus: Live

Job Summary

Seeking an ASIC/SoC design engineer to drive microarchitectural design and RTL implementation for Adaptive SoC and FPGA configuration systems. Collaborate across hardware, firmware, and software teams, and lead from concept to production silicon including timing analysis, DFT, and power/area optimization. Strong Verilog/SystemVerilog, SDC constraints, and AMBA protocols experience are required.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Author detailed micro-architecture specification and own RTL implementation of next-gen FPGA Configuration controller.
  • •Collaborate with hardware, firmware, and software teams to ensure a robust and cohesive configuration solution.
  • •Drive design from concept through production silicon across all phases: specification, RTL coding, lint/CDC checks, synthesis, timing analysis, verification, physical design integration, and post-silicon validation.
  • •Integrate complex configuration blocks into full-chip environment, ensuring proper connectivity, clock domain crossings, power domain crossing
  • •Partner with verification teams to ensure comprehensive functional coverage.

Key Requirements

  • •ASIC design experience
  • •Proficiency with Verilog and SystemVerilog (including SVA)
  • •Experience writing and debugging SDC timing constraints (multi-cycle, false paths, clock domain crossing)
  • •Familiarity with industry-standard ASIC CAD tools for simulation, synthesis, STA, LINT, LEC, CDC, RDC and power estimation
  • •Experience with AMBA AXI/AXI-S/APB and multiple power domains/UFP/scripting (Perl, Python, Makefile)
Experience:SemiconductorASICSoCFPGA
Education:Bachelor's
Skills:VerilogSystemVerilogSVASDCAMBA AXIAPBUPFPer lPythonMakefileSynthesisSTALINTLECCDCRDC
Languages:English
Tech Stack:VerilogSystemVerilogSVASDCAMBA AXIAPBUPFPerlPythonMakefileSynthesisSTALINTLECCDCRDC

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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