IP Verification Engineer
San Jose
Workplace: HybridFull timeFunction: Software EngineeringEducation: bachelorsSkills: ["Verilog","SystemVerilog","UVM","Python","Perl","PCIe","CXL","NVMe","Ethernet","Scripting"]Verification engineer in AMD’s AECG Group working on FPGA/ASIC design and verification. Collaborates with architecture, IP design, PD, and product teams to achieve first-pass silicon success, develops UVM testbenches, builds directed and random tests, runs regressions, and troubleshoots test failures to ensure functional and performance quality across complex IP architectures.
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