Pre‑Silicon Power Modeling Leader — x86 SoCs

AMD
Austin
Workplace: HybridFull timeFunction: Energy & Utilities OperationsEducation: mastersSkills: ["Communication","Collaboration","Problem-solving","Attention to detail"]

Lead SoC-level pre-silicon power modeling for AMD’s embedded and client x86 programs. Own the methodology, models, and cross‑functional influence to deliver accurate Perf/Watt projections, DVFS/AVFS plans, and silicon correlation that de-risks program power budgets. Define use‑case power envelopes, drive telemetry requirements, and collaborate with Architecture, RTL/Design, Physical Design, FW/BIOS, and System PnP to ensure converged Perf/Watt outcomes across CPU, GPU, NPU, and memory subsystems.

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FursaFursa
AMD
AMD
7 months ago

Pre‑Silicon Power Modeling Leader — x86 SoCs

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Last checked: 12 hours agoStatus: Live

Job Summary

Lead SoC-level pre-silicon power modeling for AMD’s embedded and client x86 programs. Own the methodology, models, and cross‑functional influence to deliver accurate Perf/Watt projections, DVFS/AVFS plans, and silicon correlation that de-risks program power budgets. Define use‑case power envelopes, drive telemetry requirements, and collaborate with Architecture, RTL/Design, Physical Design, FW/BIOS, and System PnP to ensure converged Perf/Watt outcomes across CPU, GPU, NPU, and memory subsystems.
Location: Austin
Workplace: Hybrid
Employment Type: Full time
Job Function: Energy & Utilities Operations
Seniority: Manager level

Key Responsibilities

  • •Own the SoC power model end‑to‑end using AMD’s converged methodology, delivering accurate workload‑based power estimates for CPU/GPU/NPU, fabric/interconnect, memory, and I/O
  • •Define use‑case power envelopes across automotive, networking, storage, industrial, and robotics segments; partner with product/marketing to derive representative workloads and KPIs
  • •Drive DVFS/AVFS strategy (P‑states, C‑states, voltage/frequency points), telemetry requirements, and FW hand‑offs based on model outputs; provide early tables and guardrails to FW/BIOS
  • •Establish IP/subsystem power budgets; run sensitivity studies to guide architectural decisions (e.g., cache sizes, fabric frequencies, NPU/GPU configurations)
  • •Build repeatable model‑to‑silicon correlation plans (CaC/static/dynamic splits, EDC/TDC interactions, droop mitigation) and maintain a power scorecard for program reviews

Key Requirements

  • •Demonstrated experience building top‑level SoC power models with high correlation to silicon, including IP‑level VBM integration and workload‑based projections
  • •Hands‑on with EDA/tooling: PowerArtist, PrimeTime PX (or equivalents), activity annotation (FSDB/VCD), UPF/CPF power intent, Python for automation
  • •Deep knowledge of x86 micro‑architecture (CPU pipelines, caches), GPU/NPU basics, memory subsystems, interconnect/fabric behavior, and power delivery/PDN interactions
  • •Proven ability to define DVFS/AVFS strategies and drive FW telemetry requirements; familiarity with EDC/TDC/CaC semantics and their impact on power
  • •A validated SoC power model & scorecard that anchors program power budgets and executive reviews
Experience:SemiconductorSoCEmbedded systemsPower modeling
Education:Master's
Skills:CommunicationCollaborationProblem-solvingAttention to detail
Languages:English
Tech Stack:PowerArtistPrimeTime PXFSDBVCDUPFCPFPythonX86DVFSAVFS

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
WebsiteLinkedIn