FuriosaAI

3 weeks ago

Silicon Validation Team Lead (NPU SoC)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 9 hours agoStatus: Live

Job Summary

Lead silicon validation for NPU SoCs from 1st bring-up through system-level performance optimization and stability. Drive pre- and post-silicon validation planning (emulator/FPGA and silicon), create bare-metal test firmware, and manage coverage. Own system-level HW/SW co-debugging and workaround delivery across RTL and firmware/driver boundaries. Support performance validation, and build test automation integrated with CI/CD to improve validation efficiency.

Location: Seoul

Workplace: Onsite

Employment Type: Full time

Job Function: Administration & Executive Assistance

Seniority: Manager level

Key Responsibilities

•Lead NPU 1st silicon bring-up by validating core subsystems (accelerator cores, CPU subsystem, NoC) and scenario-based functionality.
•Establish and run validation methodology across emulator/FPGA (pre-silicon) and silicon (post-silicon), including test plan and coverage management.
•Create bare-metal test firmware and develop test scenarios for validating each IP block.
•Perform system-level issue debugging at the HW(RTL) and SW(Firmware/Driver) boundary using JTAG/Trace32, then produce workarounds and report to stakeholders.
•Drive performance validation and optimization and implement test automation (scripts plus CI/CD integrated validation environments).

Key Requirements

•Plan and lead NPU generation bring-up and validation roadmap with strong execution and scheduling.
•Coordinate cross-functional teams (Design, DV, Firmware/Software, QA) and drive technical decision-making.
•Develop and debug in bare-metal environments using Embedded C/C++ and Rust for hardware control and IP testing.
•Apply validation methodology end-to-end: test plan creation, bug tracking, and coverage management across pre- and post-silicon.
•Demonstrate system debugging expertise using JTAG/Trace32 and strong HW/SW co-debugging and problem-solving skills.

Experience:SoCASICSilicon validationSystem validationNPUMulticore SoCPre-silicon validationPost-silicon validation

Skills:LeadershipMentoringCross-functional communicationTechnical decision-makingProblem-solving

Tech Stack:NPUSilicon ValidationTape-outRTLDVFirmwareOSSoCASICSilicon bring-upValidation roadmapEmulatorFPGATest PlanTest FirmwareBare-metalMemory SubsystemLPDDRHBMHigh-Speed I/F

Company Brief

FuriosaAI

Designs and develops data‑center AI inference accelerators (RNGD) and a full stack hardware‑software platform to deliver energy‑efficient, high‑performance AI compute for enterprise and cloud customers.

Industry: Hardware Devices

Company Size: Medium (51 to 250 employees)

Growth: Scaleup

Valuation: USD 500M to 1B

Funding: Series C

Headquarters: Seoul, South Korea

Founded: 2017

Glassdoor: 4.6

Website LinkedIn Glassdoor

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FuriosaAI

3 weeks ago

Silicon Validation Team Lead (NPU SoC)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 9 hours agoStatus: Live

Job Summary

Location: Seoul

Workplace: Onsite

Employment Type: Full time

Job Function: Administration & Executive Assistance

Seniority: Manager level

Key Responsibilities

•Lead NPU 1st silicon bring-up by validating core subsystems (accelerator cores, CPU subsystem, NoC) and scenario-based functionality.
•Establish and run validation methodology across emulator/FPGA (pre-silicon) and silicon (post-silicon), including test plan and coverage management.
•Create bare-metal test firmware and develop test scenarios for validating each IP block.
•Perform system-level issue debugging at the HW(RTL) and SW(Firmware/Driver) boundary using JTAG/Trace32, then produce workarounds and report to stakeholders.
•Drive performance validation and optimization and implement test automation (scripts plus CI/CD integrated validation environments).

Key Requirements

•Plan and lead NPU generation bring-up and validation roadmap with strong execution and scheduling.
•Coordinate cross-functional teams (Design, DV, Firmware/Software, QA) and drive technical decision-making.
•Develop and debug in bare-metal environments using Embedded C/C++ and Rust for hardware control and IP testing.
•Apply validation methodology end-to-end: test plan creation, bug tracking, and coverage management across pre- and post-silicon.
•Demonstrate system debugging expertise using JTAG/Trace32 and strong HW/SW co-debugging and problem-solving skills.

Experience:SoCASICSilicon validationSystem validationNPUMulticore SoCPre-silicon validationPost-silicon validation

Skills:LeadershipMentoringCross-functional communicationTechnical decision-makingProblem-solving

Tech Stack:NPUSilicon ValidationTape-outRTLDVFirmwareOSSoCASICSilicon bring-upValidation roadmapEmulatorFPGATest PlanTest FirmwareBare-metalMemory SubsystemLPDDRHBMHigh-Speed I/F

Company Brief

FuriosaAI

Industry: Hardware Devices

Company Size: Medium (51 to 250 employees)

Growth: Scaleup

Valuation: USD 500M to 1B

Funding: Series C

Headquarters: Seoul, South Korea

Founded: 2017

Glassdoor: 4.6

Website LinkedIn Glassdoor