Methodology Engineer – Static RTL Verification

AMD
San Jose
Workplace: OnsiteFull timeFunction: Software EngineeringEducation: bachelorsSkills: ["Communication","Collaboration","Analytical thinking","Ownership","Teamwork"]

Plan, develop, and maintain AMD EDA tools focused on RTL static checks and supporting frameworks used across AMD SoC teams to ensure high-quality RTL design. You will collaborate with RTL, verification, and methodology groups to integrate tooling into frontend and verification workflows, build automation, and reporting to improve regression efficiency and debuggability, and support SystemVerilog, UPF, and static analysis workflows.

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FursaFursa
AMD
AMD
3 months ago

Methodology Engineer – Static RTL Verification

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Source: Company careers pageValidated by: Fursa AI
Last checked: 8 hours agoStatus: Live

Job Summary

Plan, develop, and maintain AMD EDA tools focused on RTL static checks and supporting frameworks used across AMD SoC teams to ensure high-quality RTL design. You will collaborate with RTL, verification, and methodology groups to integrate tooling into frontend and verification workflows, build automation, and reporting to improve regression efficiency and debuggability, and support SystemVerilog, UPF, and static analysis workflows.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Software Engineering

Key Responsibilities

  • •Lead and contribute to the development and qualification of a static RTL quality checking tool, with a focus on production-ready quality and scalability
  • •Collaborate closely with RTL, verification, and methodology teams to integrate the tool into frontend and verification workflows
  • •Design and execute tool qualification regressions across complex AMD SoC designs, ensuring correctness across use cases and configurations
  • •Build and maintain automation, infrastructure, and reporting to improve regression efficiency and debuggability
  • •Support frontend, static, and power aware design flows, including SystemVerilog, UPF, SDC timing constraints, and static analysis tools (Lint, CDC, RDC, LEC, VCLP/CLP, Fishtail TC M)

Key Requirements

  • •Bachelor's or master's degree in Electronics Engineering or Computer Engineering (or equivalent practical experience)
  • •Strong experience with SystemVerilog and UPF
  • •Proficiency in scripting languages such as Python, Perl, Tcl, or shell
  • •Experience with RTL lint, CDC, low-power static analysis, or related verification methodologies
  • •Designing and executing tool qualification regressions across complex SoC designs and building automation to improve regression efficiency and debuggability
Experience:SemiconductorsEDARTLASIC
Education:Bachelor's
Skills:CommunicationCollaborationAnalytical thinkingOwnershipTeamwork
Languages:English
Tech Stack:SystemVerilogUPFVerilogVHDLPythonPerlTclShellLinux

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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