R&D Physical Design Engineer

Broadcom
Shanghai
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Education: mastersSkills: ["Communication","Problem solving"]

Implement and support ASIC physical design work across block and top-level tasks, including floorplanning, placement, design closure, and signoff activities such as STA, DRC, and LVS. Develop deep expertise in the full signoff flow and, where needed, drive full chip signoff runs including PI, SI, PV, and STA. Work independently, using strong VLSI ASIC design flow knowledge and scripting capability in Perl/Tcl, while collaborating on problem-solving and communication.

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FursaFursa
Broadcom
Broadcom
2 months ago

R&D Physical Design Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 7 days agoStatus: Live
Reposted: similar role first listed 5 months ago

Job Summary

Implement and support ASIC physical design work across block and top-level tasks, including floorplanning, placement, design closure, and signoff activities such as STA, DRC, and LVS. Develop deep expertise in the full signoff flow and, where needed, drive full chip signoff runs including PI, SI, PV, and STA. Work independently, using strong VLSI ASIC design flow knowledge and scripting capability in Perl/Tcl, while collaborating on problem-solving and communication.
Location: Shanghai
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Perform physical design implementation including floorplanning, placement, design closure, STA, and DRC & LVS.
  • •Develop broad physical-design skill coverage across the listed physical design areas.
  • •Support/execute full chip signoff tasks such as PI, SI, PV, and STA.
  • •Independently handle block implementation and top-level physical design tasks.
  • •Contribute to DFT insertion, power/IVD analysis, STA, and/or DRC/LVS as needed.

Key Requirements

  • •Strong understanding of the ASIC design flow and solid VLSI background.
  • •Ability to handle block implementation and top-level tasks independently.
  • •Experience running full chip signoff tasks including PI, SI, PV, and STA is better.
  • •Tapeout experience in 7nm and advanced blow process design.
  • •Strong communication and problem-solving skills, plus familiarity with DFT insertion, Power/IVD analysis, DRC/LVS, and/or STA is a plus.
Experience:ASICVLSISignoffTapeout
Education:Master's in Microelectronics or related discipline
Skills:CommunicationProblem solving
Tech Stack:PerlTcl

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn