Senior ASIC Design Engineer

Cisco
San Jose
Workplace: OnsiteFull timeUSD 167,700 - 245,200 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 7+ yearsSkills: ["Communication"]

Design and implement ASIC RTL, author design specifications, and participate in micro-architecture reviews. You’ll implement Verilog/SystemVerilog for timing, performance, and power, develop and analyze functional coverage, and partner with verification and physical design teams to resolve corner cases, achieve coverage closure, and fix place-and-route timing issues. You’ll also perform diagnostic and post-silicon validation in the lab for production-ready hardware.

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FursaFursa
Cisco
Cisco
21 hours ago

Senior ASIC Design Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 21 hours agoStatus: Live

Job Summary

Design and implement ASIC RTL, author design specifications, and participate in micro-architecture reviews. You’ll implement Verilog/SystemVerilog for timing, performance, and power, develop and analyze functional coverage, and partner with verification and physical design teams to resolve corner cases, achieve coverage closure, and fix place-and-route timing issues. You’ll also perform diagnostic and post-silicon validation in the lab for production-ready hardware.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Author design specifications and participate in micro-architecture specification reviews.
  • •Implement Verilog RTL to meet timing, performance, and power requirements.
  • •Develop and analyze functional coverage and collaborate with verification to close coverage and address corner cases.
  • •Work with physical design teams to resolve design timing and place-and-route issues.
  • •Perform diagnostic and post-silicon validation tests in the lab.

Pay and Benefits

Salary: USD 167,700 - 245,200 annually
Equity and Bonus:Equity
Perks:Health InsuranceDentalVision401kParental LeaveLong-term DisabilityBasic LifePaid LeaveEquity

Key Requirements

  • •Bachelor’s degree in Electrical or Computer engineering with 7+ years of ASIC Design experience, or Master’s degree with 4+ years, or PhD with 1+ year.
  • •Experience with Verilog/System Verilog for ASIC RTL implementation.
  • •Strong RTL skills with timing closure, power, clock gating, and the full ASIC design flow.
  • •At least one full ASIC tapeout (advanced nodes preferred).
  • •Solid debug and scripting skills.
Experience:7+ yearsASIC designTapeoutRTL
Education:
Skills:Communication
Tech Stack:VerilogSystem VerilogRTLASICFunctional coverageClock gatingPlace-and-routeTiming closurePower

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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