Senior System Integration Engineer, Memory

NVIDIA
Santa Clara, Texas, Washington, Idaho
Workplace: HybridFull timeUSD 196,000 - 310,500 annuallyFunction: Solutions Engineering & Sales EngineeringExperience: 12+ yearsEducation: bachelorsSkills: ["Engineering judgment","Cross-domain collaboration","Inventiveness","Root cause analysis","System-level problem solving"]

Own HBM and LPDDR system integration and bringup for next-generation SoCs, driving memory performance, power management, thermal, and reliability closure from silicon through package, board, and firmware. Lead post-silicon margining and correlation (VF shmoo, eye diagrams) across voltage, temperature, and frequency, then debug memory training/calibration and SI/PI stability issues. Define validation/characterization planning to ensure right tests, data, and release criteria at scale.

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FursaFursa
NVIDIA
NVIDIA
16 hours ago

Senior System Integration Engineer, Memory

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Source: Company careers pageValidated by: Fursa AI
Last checked: 16 hours agoStatus: Live

Job Summary

Own HBM and LPDDR system integration and bringup for next-generation SoCs, driving memory performance, power management, thermal, and reliability closure from silicon through package, board, and firmware. Lead post-silicon margining and correlation (VF shmoo, eye diagrams) across voltage, temperature, and frequency, then debug memory training/calibration and SI/PI stability issues. Define validation/characterization planning to ensure right tests, data, and release criteria at scale.
Location: Santa Clara, Texas, Washington, Idaho
Workplace: Hybrid
Employment Type: Full time
Job Function: Solutions Engineering & Sales Engineering
Seniority: Mid level

Key Responsibilities

  • •Drive HBM/LPDDR integration, bringup, characterization, and debug across the full arc from first silicon to production-ready at scale.
  • •Own memory performance, power management, thermal, and reliability closure across silicon, package, board, and firmware to produce signed-off operating points and release criteria.
  • •Lead post-silicon margining, VF shmoo, eye, and correlation work across voltage, temperature, and frequency.
  • •Debug memory training and calibration, SI/PI, and system-level stability issues.
  • •Define validation/characterization and issue-tracking plans across chip programs to ensure sufficient data and fidelity for closure.

Pay and Benefits

Salary: USD 196,000 - 310,500 annually
Equity and Bonus:Equity

Key Requirements

  • •BS or MS in EE/CE or equivalent experience.
  • •12+ years in HBM, LPDDR, or high-speed memory systems with hands-on depth in silicon bringup, characterization, and debug at scale.
  • •Deep command of SI/PI, timing, margining, and memory training behavior.
  • •Cross-functional fluency working across design, package, firmware, validation, and product teams.
  • •HBM PHY and controller architecture familiarity is useful; PHY controller development experience is a plus.
Experience:12+ yearsHBMLPDDRHigh-speed memory systemsSilicon bringupCharacterizationDebug
Education:Bachelor's in EE/CE
Skills:Engineering judgmentCross-domain collaborationInventivenessRoot cause analysisSystem-level problem solving
Tech Stack:HBMLPDDRSI/PIVF shmooEye diagramsLLMML modelsJEDECECCThermal-electrical co-simMargining

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
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