Lead Design Engineer

Cadence Design Systems
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 6-10 yearsEducation: bachelorsSkills: ["Verilog","SystemVerilog","UVM","Verilog-A?","Scripting","Debugging","Flow development"]

Lead the IP integration, verification, and release of Cadence SSG IPs in a Bangalore-based team. The role covers RTL integration, PHY/controller subsystem assembly, and adding features to RTL, ensuring customer configurations pass verification regressions and design cleanups per LINT and CDC guidelines. Requires expertise in ASIC flows (Lint/CDC/Synthesis/STA), Verilog, SystemVerilog, and debugging/flow development, with customer support in scope.

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FursaFursa
Cadence Design Systems
Cadence Design Systems
1 year ago

Lead Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 12 hours agoStatus: Live
Reposted: similar role first listed 1 year ago

Job Summary

Lead the IP integration, verification, and release of Cadence SSG IPs in a Bangalore-based team. The role covers RTL integration, PHY/controller subsystem assembly, and adding features to RTL, ensuring customer configurations pass verification regressions and design cleanups per LINT and CDC guidelines. Requires expertise in ASIC flows (Lint/CDC/Synthesis/STA), Verilog, SystemVerilog, and debugging/flow development, with customer support in scope.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Manager level

Key Responsibilities

  • •IP integration for Cadence IPs and release engineering within the SSG IP Release team
  • •Verify integrated RTL and PHY/controller subsystems and ensure configurations pass verification regressions
  • •Develop and debug ASIC flows (Lint, CDC, Synthesis, STA) and set up new flows
  • •Collaborate with RTL teams to add features to RTL and maintain design cleanliness
  • •Provide customer support and ensure designs adhere to LINT and CDC guidelines

Key Requirements

  • •6-10 years of core RTL integration and verification experience using Verilog
  • •SystemVerilog experience and experience with UVM based environment usage / debugging
  • •PCIe/CXL/IDE experience highly desirable; prior experience in implementation of complex protocols
  • •BE/BTech/ME/MTech - Electrical / Electronics / VLSI with experience as a design verification engineer
  • •Scripting knowledge is an advantage
Experience:6-10 yearsRTL integrationVerificationASICVerilogSystemVerilogUVM
Education:Bachelor's
Skills:VerilogSystemVerilogUVMVerilog-A?ScriptingDebuggingFlow development
Languages:English
Tech Stack:VerilogSystemVerilogUVMGenusLintCDCSynthesisSTAPCIeCXL

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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