Functional Verification Engineer - Applied ML

Cadence Design Systems
Israel
Workplace: OnsiteFull timeFunction: Administration & Executive AssistanceExperience: 4+ yearsEducation: bachelorsSkills: ["Communication","Teamwork","Collaboration","Problem-solving"]

Lead pre-silicon verification efforts at Cadence, applying machine learning techniques to streamline formal verification and UVM-based methods. Collaborate with ML and software teams to deploy agentic AI solutions, engage customers for requirements, and stay ahead of AI-powered hardware verification advancements, inside a team driving the ChipStack AI Super Agent platform to autonomous chip design and verification.

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Cadence Design Systems
Cadence Design Systems
5 months ago

Functional Verification Engineer - Applied ML

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Source: Company careers pageValidated by: Fursa AI
Last checked: 3 hours agoStatus: Live

Job Summary

Lead pre-silicon verification efforts at Cadence, applying machine learning techniques to streamline formal verification and UVM-based methods. Collaborate with ML and software teams to deploy agentic AI solutions, engage customers for requirements, and stay ahead of AI-powered hardware verification advancements, inside a team driving the ChipStack AI Super Agent platform to autonomous chip design and verification.
Location: Israel
Workplace: Onsite
Employment Type: Full time
Job Function: Administration & Executive Assistance

Key Responsibilities

  • •Contribute to the application of machine learning techniques aimed at streamlining traditional pre-silicon functional verification methodologies like formal verification and UVM.
  • •Develop agentic AI solutions using LLMs and latest ML technologies to accelerate pre-silicon Design Verification process.
  • •Employ AI enhanced Electronic Design Automation (EDA) tools to improve and expedite both the design and verification lifecycles.
  • •Engage directly with customers to understand requirements and deliver innovative, practical verification strategies.
  • •Collaborate effectively with machine learning and software engineering teams to validate output correctness, efficiency, and quality.

Key Requirements

  • •BS with a minimum of 4 years of experience OR MS with a minimum of 2 years of experience OR new PhD Graduate
  • •Proven expertise of more than 3 years in at least one of the pre-silicon ASIC verification methodologies such as Formal, SV/UVM and/or OVM
  • •Advanced skills in debugging pre-silicon verification failures using waveform viewers and simulation analysis tools
  • •Hands-on experience with industry standard EDA tools (e.g., Jasper, Xcelium, IMC)
  • •Strong programming skills in Verilog, System Verilog and Python
Experience:4+ yearsSemiconductorAI
Education:Bachelor's
Skills:CommunicationTeamworkCollaborationProblem-solving
Tech Stack:VerilogSystemVerilogPythonUVMJasperXceliumIMCFormal verificationLLMsAI

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
Glassdoor
Glassdoor: 3.9
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