Analog Mixed Signal Design Engineer
Intel
Canada
Workplace: RemoteFull timeCAD 129,740 - 183,170 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 2+ yearsEducation: bachelorsSkills: ["Cadence ADE","Python","Verilog-A","SystemVerilog"]Join Intel’s mixed-signal IP development team as a Senior Mixed Signal Design Engineer. You will lead static timing analysis and design closure across analog-digital interfaces, perform analog circuit design and verification with Cadence ADE, and collaborate with design and RTL teams to accelerate silicon success in a fast-paced environment.
