Sr Principal Design Engineer

Cadence Design Systems
Noida
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 10+ yearsEducation: bachelorsSkills: ["UVM","SystemVerilog","Verification","Debug","Testbench","Emulation","Formal verification"]

Design verification for IP development in Cadence IP Group, focusing on Serial and Interface Design IP verification (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C). Develop UVM testbenches, with potential formal verification and emulation qualification, and craft detailed verification strategies and test plans across Bangalore/Noida teams.

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Cadence Design Systems
Cadence Design Systems
7 months ago

Sr Principal Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 19 hours agoStatus: Live

Job Summary

Design verification for IP development in Cadence IP Group, focusing on Serial and Interface Design IP verification (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C). Develop UVM testbenches, with potential formal verification and emulation qualification, and craft detailed verification strategies and test plans across Bangalore/Noida teams.
Location: Noida
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Director level

Key Responsibilities

  • •Design verification for IP development within the IP verification team.
  • •Verify Serial and Interface Design IPs (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C) to ensure correct operation.
  • •Develop robust UVM testbenches to verify IP designs and ensure scalability and efficiency of the verification environment.
  • •Perform formal verification of complex design modules as needed and participate in emulation qualification of design IPs.
  • •Produce and maintain detailed verification strategy and test plans, communicating progress and issues clearly across teams.

Key Requirements

  • •B. Tech/M.Tech with 10+ years of relevant experience.
  • •Verification role for Serial and Interface Design IPs verification (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C).
  • •UVM testbench development to build a robust, scalable and efficient testbench to verify the design IPs.
  • •Formal verification of complex design modules may be involved.
  • •Emulation qualification of design IPs may be involved.
Experience:10+ yearsSemiconductorHardware designIP verification
Education:Bachelor's
Skills:UVMSystemVerilogVerificationDebugTestbenchEmulationFormal verification
Tech Stack:UVMSystemVerilogPCIeCCIXCXLUSBEthernetSATASASUFSSPIHDMIMIPII3C

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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