Principal Software Engineer - Compiler Development

Cadence Design Systems
Burlington
Workplace: OnsiteFull timeUSD 117,600 - 218,400 annuallyFunction: Software EngineeringExperience: 5+ yearsSkills: ["Problem-solving","Innovation","Performance optimization","Scalability thinking"]

Develop and evolve the Xcelium logic simulator compiler and code generator, focusing on scalable intermediate representations for extremely large chip designs. Lead language extension work for SystemVerilog, optimize compilation performance in C/C++, and architect compiler/simulator components for complex AI and hyperscale workloads. Prototype next-gen capabilities such as LLM-enhanced and parallel/distributed compilation, while applying deep compiler theory and performance engineering to reduce time-to-market.

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Cadence Design Systems
Cadence Design Systems
7 hours ago

Principal Software Engineer - Compiler Development

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Source: Company careers pageValidated by: Fursa AI
Last checked: 7 hours agoStatus: Live

Job Summary

Develop and evolve the Xcelium logic simulator compiler and code generator, focusing on scalable intermediate representations for extremely large chip designs. Lead language extension work for SystemVerilog, optimize compilation performance in C/C++, and architect compiler/simulator components for complex AI and hyperscale workloads. Prototype next-gen capabilities such as LLM-enhanced and parallel/distributed compilation, while applying deep compiler theory and performance engineering to reduce time-to-market.
Location: Burlington
Workplace: Onsite
Employment Type: Full time
Job Function: Software Engineering
Seniority: Mid level

Key Responsibilities

  • •Design and implement advanced SystemVerilog language extensions.
  • •Develop and optimize high-performance compiler front-end and code generation components using scalable intermediate representations (IR).
  • •Perform bottleneck analysis and implement performance optimizations to improve compilation speed and memory footprint.
  • •Architect compiler and simulator capabilities tuned for complex AI designs, including massively replicated and parallel structures.
  • •Explore and prototype next-generation features such as LLM-enhanced compilation, parallel compilation, and distributed compilation.

Pay and Benefits

Salary: USD 117,600 - 218,400 annually
Equity and Bonus:Equity
Perks:Paid LeavePaid Holidays401kHealth InsuranceDentalVision

Key Requirements

  • •BS with 10+ years, or MS with 7+ years, or PhD with 5+ years of experience.
  • •5+ years in compiler development, EDA, or high-performance computing.
  • •Expert-level C++ (modern standards) with deep understanding of SystemVerilog or Verilog.
  • •Proven experience in compiler theory including lexing, parsing, semantic analysis, and code generation.
  • •Experience with multi-threading, memory management, and cache-locality performance optimizations.
Experience:5+ yearsEDAHigh-performance computing
Skills:Problem-solvingInnovationPerformance optimizationScalability thinking
Tech Stack:SystemVerilogVerilogC++CLLVMPythonUVMLLMs

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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