SoC/IP Design Verification Engineer

Intel
Mexico, Costa Rica
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: ["Problem-solving","Collaboration","Learning agility","Attention to detail","Results orientation"]

Own verification planning and execution for complex SoC/IP blocks, from requirements decomposition and coverage strategy to signoff. Architect and build reusable UVM/SystemVerilog verification environments, develop constrained-random and directed test content, and drive functional/code coverage closure. Debug failures across simulation and emulation using assertions, waveforms, and reference models, while collaborating with RTL, architecture, firmware, DV/DFT, and post-silicon validation teams to deliver silicon on schedule.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Intel
Intel
1 month ago

SoC/IP Design Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 56 minutes agoStatus: Live

Job Summary

Own verification planning and execution for complex SoC/IP blocks, from requirements decomposition and coverage strategy to signoff. Architect and build reusable UVM/SystemVerilog verification environments, develop constrained-random and directed test content, and drive functional/code coverage closure. Debug failures across simulation and emulation using assertions, waveforms, and reference models, while collaborating with RTL, architecture, firmware, DV/DFT, and post-silicon validation teams to deliver silicon on schedule.
Location: Mexico, Costa Rica
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Own the verification lifecycle for one or more IPs/subsystems/SoC top-level features, including requirements decomposition, test plan definition, coverage strategy, execution, and signoff.
  • •Architect and implement UVM environments with reusable agents, drivers, monitors, sequencers, scoreboards, and reference models.
  • •Develop test content using constrained-random sequences, scenario tests, stimulus libraries, checkers, and assertions.
  • •Debug failures quickly and methodically across simulation and emulation using waveforms, logs, assertions, checkers, and reference model comparisons.
  • •Drive functional and code coverage closure and strengthen verification quality using assertions (SVA) and formal where appropriate.

Key Requirements

  • •Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
  • •5+ years of SoC/IP design verification experience.
  • •UVM/SystemVerilog development including testbenches, agents, scoreboards, and virtual sequences.
  • •Test planning skills translating RTL/architecture specs into measurable, coverage-driven verification plans.
  • •Proven debug and automation skills across simulation/emulation, plus advance English and unrestricted, permanent right to work in Mexico (no visa/immigration sponsorship).
Experience:5+ yearsSoC/IPHardware verificationUVM
Education:Bachelor's
Skills:Problem-solvingCollaborationLearning agilityAttention to detailResults orientation
Languages:English
Tech Stack:UVMSystemVerilogSVAAXIACEPCIeDDRAXI/ACE/CHICHIUSBMIPII3CSPII2CEthernetPythonShellMakeCMakeSynopsys VCS

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
Glassdoor
Glassdoor: 3.8
WebsiteLinkedInGlassdoor