SoC/IP Design Verification Engineer

Own verification planning and execution for complex SoC/IP blocks, from requirements decomposition and coverage strategy to signoff. Architect and build reusable UVM/SystemVerilog verification environments, develop constrained-random and directed test content, and drive functional/code coverage closure. Debug failures across simulation and emulation using assertions, waveforms, and reference models, while collaborating with RTL, architecture, firmware, DV/DFT, and post-silicon validation teams to deliver silicon on schedule.