Senior RTL Design Engineer

Cisco
Armenia
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Skills: ["Communication","Self-motivated","Well-organized"]

Drive RTL and qualification work for Cisco Silicon One networking ASICs in the Common Hardware Group. You’ll collaborate with front-end RTL and back-end physical design teams to deliver high-quality Design for Test (DFT) verification, enhance and review RTL code, and streamline IP/SoC development flows. Expect cross-functional debugging on complex verification failures and continuous improvements to improve silicon reliability and performance.

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FursaFursa
Cisco
Cisco
7 months ago

Senior RTL Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 12 hours agoStatus: Live

Job Summary

Drive RTL and qualification work for Cisco Silicon One networking ASICs in the Common Hardware Group. You’ll collaborate with front-end RTL and back-end physical design teams to deliver high-quality Design for Test (DFT) verification, enhance and review RTL code, and streamline IP/SoC development flows. Expect cross-functional debugging on complex verification failures and continuous improvements to improve silicon reliability and performance.
Location: Armenia
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Participate in digital design across micro-architecture, RTL design, and qualification.
  • •Support sub-system/SoC integration and verification.
  • •Review and enhance RTL codes.
  • •Improve flows and methodologies to streamline IP/SoC development and integration.
  • •Collaborate with verification and physical design teams to resolve debug failures and improve physical design QoR.

Key Requirements

  • •5+ years of industry experience in ASIC digital design.
  • •Proficient in Verilog/SystemVerilog coding.
  • •Experience with front-end tools including Verilog simulators, linting, CDC checkers, synthesis, and formal verification.
  • •Experience with industry interface protocols such as AMBA (AXI, APB, AHB) and JTAG, plus memories.
  • •Ability to write scripts using Python, Tcl, and Make.
Experience:ASIC digital designSemiconductorsSilicon hardware
Skills:CommunicationSelf-motivatedWell-organized
Tech Stack:VerilogSystemVerilogPythonTclMakeVerilog simulatorsLintingCDC checkersSynthesisFormal verificationAMBAAXIAPBAHBJTAGMemoriesDFTUPFPower estimationMBIST

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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Glassdoor: 4.0
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