Cadence Design Systems

3 weeks ago

Principal Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 13 hours agoStatus: Live

Job Summary

Lead physical design, timing closure, and verification for ASICs/SoCs in sub-7nm processes. Drive end-to-end implementation flows from RTL to GDSII, ensure timing closure and formal verification, and collaborate on complex IPs. Proficient in Cadence tools Genus, Innovus, Quantus, Tempus, PVS, Voltus, with automation in Makefile/Tcl/Tk/Perl/Python. Strong communication and teamwork is essential.

Location: Pune

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Lead physical design, timing closure and physical verification for ASICs/SoCs.
•Work with ASIC design flow and hierarchical physical design strategies and methodologies.
•Address deep sub-micron technology issues and ensure robust timing closure.
•Contribute to complex IPs & SoCs below 7 nm with rigorous verification.
•Utilize Cadence tools Genus, Innovus, Quantus, Tempus, PVS, Voltus and automate workflows with Makefile/Tcl/Tk/Perl/Python.

Key Requirements

•BE/ BTech/ ME/ MTech / MS with 6 – 15 years of experience in physical design, timing closure and physical verification.
•Experience with ASIC design flow, hierarchical physical design strategies, methodologies and deep sub-micron technology issues.
•Solid knowledge on physical design flow, timing closure and physical verification; knowledge of formal verification, EM-IR.
•Proven track record working on complex IPs and SoCs below 7 nm.
•Power user of Cadence implementation tools: Genus, Innovus, Quantus, Tempus, PVS, Voltus; automation experience with Makefile/Tcl/Tk/Perl/Python.

Experience:6-15 yearsSemiconductorASICSoCEDACadencePhysical design

Education:Bachelor's

Skills:CommunicationTeamworkSelf-motivated

Tech Stack:Cadence GenusCadence InnovusCadence QuantusCadence TempusCadence PVSCadence VoltusMakefileTclTkPerlPython

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

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Cadence Design Systems

3 weeks ago

Principal Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 13 hours agoStatus: Live

Job Summary

Location: Pune

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Lead physical design, timing closure and physical verification for ASICs/SoCs.
•Work with ASIC design flow and hierarchical physical design strategies and methodologies.
•Address deep sub-micron technology issues and ensure robust timing closure.
•Contribute to complex IPs & SoCs below 7 nm with rigorous verification.
•Utilize Cadence tools Genus, Innovus, Quantus, Tempus, PVS, Voltus and automate workflows with Makefile/Tcl/Tk/Perl/Python.

Key Requirements

•BE/ BTech/ ME/ MTech / MS with 6 – 15 years of experience in physical design, timing closure and physical verification.
•Experience with ASIC design flow, hierarchical physical design strategies, methodologies and deep sub-micron technology issues.
•Solid knowledge on physical design flow, timing closure and physical verification; knowledge of formal verification, EM-IR.
•Proven track record working on complex IPs and SoCs below 7 nm.
•Power user of Cadence implementation tools: Genus, Innovus, Quantus, Tempus, PVS, Voltus; automation experience with Makefile/Tcl/Tk/Perl/Python.

Experience:6-15 yearsSemiconductorASICSoCEDACadencePhysical design

Education:Bachelor's

Skills:CommunicationTeamworkSelf-motivated

Tech Stack:Cadence GenusCadence InnovusCadence QuantusCadence TempusCadence PVSCadence VoltusMakefileTclTkPerlPython

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor