Senior Physical Design Engineer - Signoff Methodology

Cisco
Armenia
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: ["RTL","GDS","PnR","STA","PV","FV","Synopsys","Cadence","EDA tools"]

Join Cisco’s CAD Physical Design team in Silicon One to develop and refine backend flows from RTL to GDS, enabling high-performance, large-scale VLSI designs. You’ll advance signoff flows (physical synthesis, place & route, power, timing, physical closure), collaborate across engineering teams, and work with advanced silicon technologies to deliver complex devices from RTL to GDS.

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FursaFursa
Cisco
Cisco
7 months ago

Senior Physical Design Engineer - Signoff Methodology

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Last checked: 4 hours agoStatus: Live

Job Summary

Join Cisco’s CAD Physical Design team in Silicon One to develop and refine backend flows from RTL to GDS, enabling high-performance, large-scale VLSI designs. You’ll advance signoff flows (physical synthesis, place & route, power, timing, physical closure), collaborate across engineering teams, and work with advanced silicon technologies to deliver complex devices from RTL to GDS.
Location: Armenia
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Manager level

Key Responsibilities

  • •Develop and refine backend methodologies and flows from RTL to GDS, supporting high-quality VLSI design.
  • •Contribute to the advancement of all signoff flows, including physical synthesis, place and route, power optimization, timing closure, and physical closure.
  • •Collaborate with engineering teams to support and enhance implementation tool flows.
  • •Work with advanced silicon technologies and processes to deliver complex and reliable devices.

Key Requirements

  • •5+ years of experience as a CAD Physical Design Engineer with PnR and STA or as a Design Engineer with strong backend design experience
  • •B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering, or a related field
  • •Strong understanding of STA flows
  • •Familiarity with PnR, physical verification (PV), and formal verification (FV)
  • •Experience in Physical Design CAD, especially with industry-standard EDA tools such as Synopsys or Cadence
Experience:5+ yearsSemiconductorSiliconVLSI
Education:Bachelor's
Skills:RTLGDSPnRSTAPVFVSynopsysCadenceEDA tools
Tech Stack:RTLGDSPnRSTAPVFVSynopsysCadenceEDA tools

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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Glassdoor: 4.0
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