Senior Power Integrity Engineer - LPU Packaging

NVIDIA
Santa Clara
Workplace: OnsiteFull timeFunction: Energy & Utilities OperationsExperience: 12+ yearsEducation: mastersSkills: ["Power Integrity","PDN design","HBM","FSBGA","3D-IC","PCB","VP/VRM","LVDS","SPICE","IBIS-AMI","PowerSI","PowerDC","Sigrity","RedHawk","HFSS","SIwave","ADS"]

Lead power integrity design and validation for NVIDIA’s LPU packaging across die, package, board, and rack levels. Own PDN targets (impedance, droop, noise, transient response) for GPUs, HBMs, and high-speed SerDes; architect package-level PDNs; drive system-level PI with SI/thermal/mechanical teams; develop PI models and co-simulation flows; oversee lab validation and debug complex rail issues.

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FursaFursa
NVIDIA
NVIDIA
4 months ago

Senior Power Integrity Engineer - LPU Packaging

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Source: Company careers pageValidated by: Fursa AI
Last checked: 20 hours agoStatus: Live

Job Summary

Lead power integrity design and validation for NVIDIA’s LPU packaging across die, package, board, and rack levels. Own PDN targets (impedance, droop, noise, transient response) for GPUs, HBMs, and high-speed SerDes; architect package-level PDNs; drive system-level PI with SI/thermal/mechanical teams; develop PI models and co-simulation flows; oversee lab validation and debug complex rail issues.
Location: Santa Clara
Workplace: Onsite
Employment Type: Full time
Job Function: Energy & Utilities Operations
Seniority: Sr. Manager level

Key Responsibilities

  • •Define best‑in‑class power delivery design and optimization practices from die/package through board, tray, and rack levels for the full product development cycle
  • •Own the PI specification and methodology for assigned products, defining PDN targets including impedance, droop, noise, and transient response for GPU, HBM, and high‑speed SerDes
  • •Architect package‑level PDNs by collaborating with design teams on bump/ball maps, via structures, and decoupling strategies for FCBGA and 25D/3D integrations
  • •Drive system‑level PI design, including board‑level PDN planning, decap placement, and VRM interfaces while co-optimizing with SI, thermal, and mechanical teams
  • •Perform PI extraction and simulation for advanced packages and develop integrated chip–package–board co‑simulation flows using industry-standard tools

Pay and Benefits

Equity and Bonus:Equity
Perks:Equity

Key Requirements

  • •MS or PhD in Electrical Engineering or a related field, or equivalent experience
  • •12+ years of relevant work experience in Power Integrity
  • •strong background in power integrity for high-current, low-voltage rails within GPUs/ASICs/CPUs
  • •proven ownership of chip-package-board PDN design and sign-off process
  • •hands-on experience with FCBGA, 25D/3D integration, HBM, or similar high-power, high-pin-count packages
Experience:12+ yearsSemiconductorsHardwareAI hardware
Education:Master's
Skills:Power IntegrityPDN designHBMFSBGA3D-ICPCBVP/VRMLVDSSPICEIBIS-AMIPowerSIPowerDCSigrityRedHawkHFSSSIwaveADS
Languages:English
Tech Stack:PowerSIPowerDCSigrityRedHawkTotemHFSSSIwaveADSSPICEVNAsOscilloscopes

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
Glassdoor
Glassdoor: 4.3
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