Intel

1 month ago

Senior SoC Compute/Memory Subsystem Architect

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Lead end-to-end architecture of compute complexes, cache hierarchies, and memory subsystems for next-generation IPU/DPU platforms. Define ARM/x86 compute topologies, memory controllers, interconnects, and virtualization features, partnering with networks, storage, and accelerator teams to optimize performance, power, and programmability in hyperscale data centers and AI workloads.

Location: Santa Clara, San Jose, Austin, Phoenix

Workplace: Hybrid

Employment Type: Full time

Job Function: Solutions Engineering & Sales Engineering

Seniority: Sr. Manager level

Key Responsibilities

•Define architecture for IPU compute complexes (e.g., ARM/x86 clusters), including core selection, scaling strategy, and configuration tradeoffs; define compute subsystem roles (control plane, data plane assist, offload execution, management services).
•Define and evolve multi-level cache hierarchy and coherency models across compute cores, accelerators, and IO subsystems; evaluate latency, bandwidth, scalability, and complexity tradeoffs.
•Architect system memory subsystems (DDR/LPDDR interfaces, memory controllers, scheduling policies, bandwidth scaling) and define memory access models with performance targets.
•Define architecture for SMMU/IOMMU supporting virtualization-heavy IPU workloads and multi-tenant isolation with secure memory models.
•Architect integration between compute, network, storage, and accelerator subsystems; optimize data movement to minimize copies, latency, and bandwidth; drive long-term architecture roadmaps.

Pay and Benefits

Salary: USD 164,470 - 269,100 annually

Equity and Bonus:Equity

Key Requirements

•Bachelor's degree in Electrical Engineering, Computer Engineering, or a STEM related Field of Study.
•7+ years of experience in SoC / CPU / memory subsystem architecture and CPU architecture and cache hierarchies.
•Experience with memory subsystems (DDR/HBM, controllers, QoS) and coherent/non-coherent interconnect architectures.
•Experience in system-level performance and PPA tradeoff analysis.
•Ability to drive architecture definition from concept to silicon.

Experience:7+ yearsSemiconductorsIPUHyperscaleCloudAI

Education:Bachelor's

Skills:ARMX86DDRLPDDRHBMPCIeCXLSMMUIOMMUNUMACache coherencyDVFS

Tech Stack:ARMX86DDRLPDDRHBMPCIeCXLSMMUIOMMUNUMACache coherencyDVFSIPUDPU

Company Brief

Intel

Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1968

Glassdoor: 3.8

Website LinkedIn Glassdoor

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Intel

1 month ago

Senior SoC Compute/Memory Subsystem Architect

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Location: Santa Clara, San Jose, Austin, Phoenix

Workplace: Hybrid

Employment Type: Full time

Job Function: Solutions Engineering & Sales Engineering

Seniority: Sr. Manager level

Key Responsibilities

•Define architecture for IPU compute complexes (e.g., ARM/x86 clusters), including core selection, scaling strategy, and configuration tradeoffs; define compute subsystem roles (control plane, data plane assist, offload execution, management services).
•Define and evolve multi-level cache hierarchy and coherency models across compute cores, accelerators, and IO subsystems; evaluate latency, bandwidth, scalability, and complexity tradeoffs.
•Architect system memory subsystems (DDR/LPDDR interfaces, memory controllers, scheduling policies, bandwidth scaling) and define memory access models with performance targets.
•Define architecture for SMMU/IOMMU supporting virtualization-heavy IPU workloads and multi-tenant isolation with secure memory models.
•Architect integration between compute, network, storage, and accelerator subsystems; optimize data movement to minimize copies, latency, and bandwidth; drive long-term architecture roadmaps.

Pay and Benefits

Salary: USD 164,470 - 269,100 annually

Equity and Bonus:Equity

Key Requirements

•Bachelor's degree in Electrical Engineering, Computer Engineering, or a STEM related Field of Study.
•7+ years of experience in SoC / CPU / memory subsystem architecture and CPU architecture and cache hierarchies.
•Experience with memory subsystems (DDR/HBM, controllers, QoS) and coherent/non-coherent interconnect architectures.
•Experience in system-level performance and PPA tradeoff analysis.
•Ability to drive architecture definition from concept to silicon.

Experience:7+ yearsSemiconductorsIPUHyperscaleCloudAI

Education:Bachelor's

Skills:ARMX86DDRLPDDRHBMPCIeCXLSMMUIOMMUNUMACache coherencyDVFS

Tech Stack:ARMX86DDRLPDDRHBMPCIeCXLSMMUIOMMUNUMACache coherencyDVFSIPUDPU

Company Brief

Intel

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1968

Glassdoor: 3.8

Website LinkedIn Glassdoor