Design Verification Engineer

AMD
Santa Clara
Workplace: HybridFull timeUSD 145,600 - 249,600 annuallyFunction: Design (Product/UX/UI/Visual)Skills: ["Communication","Presentation","Collaboration","Mentoring","Knowledge sharing"]

Drive design verification for DDR memory interfaces used in server memory products. Lead verification plan execution for DDR5, LPDDR5/LPDDR6, and DFI across DIMMs, ensuring alignment between HW (silicon), FW, BIOS, and SW. Apply RTL and micro-architecture knowledge for cross-functional debug with architects and design engineers, develop SystemVerilog/UVM testbenches with coverage, and support post-si issue investigation across performance, power, and functionality.

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FursaFursa
AMD
AMD
1 month ago

Design Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 18 hours agoStatus: Live
Reposted: similar role first listed 7 months ago

Job Summary

Drive design verification for DDR memory interfaces used in server memory products. Lead verification plan execution for DDR5, LPDDR5/LPDDR6, and DFI across DIMMs, ensuring alignment between HW (silicon), FW, BIOS, and SW. Apply RTL and micro-architecture knowledge for cross-functional debug with architects and design engineers, develop SystemVerilog/UVM testbenches with coverage, and support post-si issue investigation across performance, power, and functionality.
Location: Santa Clara
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Develop and execute verification plans for DDR5, LPDDR5, and DFI memory systems in server products.
  • •Analyze PHY interaction across HW (silicon), FW, BIOS, and SW and ensure FW/BIOS/SW alignment for memory interface features.
  • •Understand RTL and micro-architecture to participate in cross-functional discussions for planning and debug.
  • •Contribute to verification methodology through knowledge sharing and other improvements.
  • •Support post-silicon teams with product performance, power, and functional issue debug and resolution.

Pay and Benefits

Salary: USD 145,600 - 249,600 annually

Key Requirements

  • •Experience with SystemVerilog and UVM to build testbenches, simulation environments, and functional coverage models for DDR5 and LPDDR5.
  • •Verification of DDR5, LPDDR5, and DFI memory systems in server products, including execution of verification plans with a team.
  • •Strong understanding of RTL and micro-architecture for cross-functional planning and debug with IP/domain and design engineers.
  • •Ability to comprehend PHY interaction across HW (silicon), FW, BIOS, and SW to ensure alignment enabling memory interface features.
  • •Excellent communication, presentation, collaboration skills, and readiness to mentor and guide others.
Education:
Skills:CommunicationPresentationCollaborationMentoringKnowledge sharing
Tech Stack:SystemVerilogUVMDDR5LPDDR5LPDDR6DFIDIMMsCC++PythonPerlRTLFunctional coverageSystemVerilog assertionsConstraintsFormal verificationVIPsBFMsBIOSFW

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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