Chiplet Verification Lead

Lead verification efforts for next-generation chiplet SoC designs, developing scalable, reusable SystemVerilog/UVM testbenches and driving verification strategy and planning for complex server-class architectures. Build and deploy SystemVerilog Assertions and apply formal verification (property checking, formal exploration) to critical blocks. Collaborate with RTL, DFT, validation, firmware, and physical design teams, manage coverage closure, and mentor engineers while documenting results for continuous improvement.