Cisco

2 months ago

ASIC Engineering Technical Leader- STA

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 1 hour agoStatus: Live

Job Summary

Lead architecture, design, and verification of high-performance ASICs and subsystems for Cisco platforms. Drive STA integration, timing closure, and parasitic analysis across advanced nodes, guiding mixed-signal and physical design while establishing reusable methodologies and verification strategies within a mult-disciplinary hardware team.

Location: San Jose

Workplace: Onsite

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Key Responsibilities

•Oversees the definition, architecture and design of high performance ASICs; guides verification strategy and code methodologies for reusable code; ensures robust design practices across the project.
•Oversees all applications and code including methodology of reusable code; defines coding approaches and standards across teams.
•Consults for architecture and design decisions for complex areas; drives design solutions across the business.
•Creates guidelines and standards; oversees system-level verification using test benches and code reviews.
•Architects and designs analog/mixed-signal circuits; reviews complex IC designs and leads improvements.

Pay and Benefits

Salary: USD 210,600 - 305,100 annually

Equity and Bonus:Equity

Perks:Health Insurance401kEquity

Key Requirements

•Bachelor’s degree with 10+ years related experience, or Master’s with 5+ years, or PhD with 2+ years (minimum).
•Experience with Integration for STA including hyperscale and hierarchical analysis with parasitic stitching, IO budgeting, and flat parasitic extraction.
•Experience in developing timing constraints and signing off timing on blocks/subsystems in advanced process nodes.
•Experience with timing closure including transition, setup, hold, noise, crosstalk, and power recovery.
•Experience with various on-chip variations including AOCV, POCV and voltage, temperature, aging-based timing derates.

Experience:SemiconductorASICSilicon

Education:Bachelor's

Skills:SynopsysCadenceTCLPerlPythonStar-RCXTFormalityLECPrimetimeTweakerPrimeTimeCadence TempusParasitic Extraction

Tech Stack:SynopsysCadenceTCLPerlPythonStar-RCXTPrimetimeTempusFormalityLECParasitic Extraction

Company Brief

Cisco

Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.

Industry: Networking Equipment

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1984

Glassdoor: 4.0

Website LinkedIn Glassdoor

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Cisco

2 months ago

ASIC Engineering Technical Leader- STA

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 1 hour agoStatus: Live

Job Summary

Location: San Jose

Workplace: Onsite

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Key Responsibilities

•Oversees the definition, architecture and design of high performance ASICs; guides verification strategy and code methodologies for reusable code; ensures robust design practices across the project.
•Oversees all applications and code including methodology of reusable code; defines coding approaches and standards across teams.
•Consults for architecture and design decisions for complex areas; drives design solutions across the business.
•Creates guidelines and standards; oversees system-level verification using test benches and code reviews.
•Architects and designs analog/mixed-signal circuits; reviews complex IC designs and leads improvements.

Pay and Benefits

Salary: USD 210,600 - 305,100 annually

Equity and Bonus:Equity

Perks:Health Insurance401kEquity

Key Requirements

•Bachelor’s degree with 10+ years related experience, or Master’s with 5+ years, or PhD with 2+ years (minimum).
•Experience with Integration for STA including hyperscale and hierarchical analysis with parasitic stitching, IO budgeting, and flat parasitic extraction.
•Experience in developing timing constraints and signing off timing on blocks/subsystems in advanced process nodes.
•Experience with timing closure including transition, setup, hold, noise, crosstalk, and power recovery.
•Experience with various on-chip variations including AOCV, POCV and voltage, temperature, aging-based timing derates.

Experience:SemiconductorASICSilicon

Education:Bachelor's

Skills:SynopsysCadenceTCLPerlPythonStar-RCXTFormalityLECPrimetimeTweakerPrimeTimeCadence TempusParasitic Extraction

Tech Stack:SynopsysCadenceTCLPerlPythonStar-RCXTPrimetimeTempusFormalityLECParasitic Extraction

Company Brief

Cisco

Industry: Networking Equipment

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1984

Glassdoor: 4.0

Website LinkedIn Glassdoor