ASIC/FPGA Design Engineer 1A

Ciena
Gurugram
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Skills: ["Collaboration","Ability to learn","Ability to work collaboratively","Apply new concepts"]

Design FPGA digital logic for new and enhanced features for Ethernet, optical, and processor peripheral applications. Own block-level verification, simulation, and laboratory validation, including qualifying functionality across thermal operating environments. Use AMD Vivado or Altera Quartus for FPGA development, develop logic in Verilog/SystemVerilog, and apply TCL or PERL scripts within workflows while collaborating with a team to deliver reliable designs.

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FursaFursa
Ciena
Ciena
5 hours ago

ASIC/FPGA Design Engineer 1A

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Source: Company careers pageValidated by: Fursa AI
Last checked: 5 hours agoStatus: Live

Job Summary

Design FPGA digital logic for new and enhanced features for Ethernet, optical, and processor peripheral applications. Own block-level verification, simulation, and laboratory validation, including qualifying functionality across thermal operating environments. Use AMD Vivado or Altera Quartus for FPGA development, develop logic in Verilog/SystemVerilog, and apply TCL or PERL scripts within workflows while collaborating with a team to deliver reliable designs.
Location: Gurugram
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Design FPGA digital logic for new features and incremental enhancements within existing IP/FPGA blocks.
  • •Perform block-level verification and simulations for FPGA designs.
  • •Utilize AMD Vivado or Altera Quartus tools during FPGA development.
  • •Validate implemented logic in laboratory environments.
  • •Qualify FPGA functionality across thermal operating environments.

Key Requirements

  • •Apply digital logic design concepts.
  • •Use Verilog/SystemVerilog for basic logic design.
  • •Use AMD Vivado or Altera Quartus for FPGA development.
  • •Use block-level verification and simulation techniques for FPGA designs.
  • •Use TCL or PERL scripts within development workflows.
Experience:FPGADigital logicEthernetOpticalASIC
Skills:CollaborationAbility to learnAbility to work collaborativelyApply new concepts
Tech Stack:VerilogSystemVerilogAMD VivadoAltera QuartusTCLPERL

Company Brief

Ciena
Provides networking systems, software, and services that enable service providers, cloud operators, and enterprises to deliver high-capacity connectivity and adaptive network solutions worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Hanover, United States
Founded: 1992
Glassdoor
Glassdoor: 3.8
WebsiteLinkedIn