Physical Design Lead with STA

AMD
Hyderabad
Workplace: OnsiteFull timeINR 3,338,160 - 4,768,800 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsEducation: bachelorsSkills: ["Collaboration","Communication","Self-driving","Organization","Automation mindset"]

Own physical design signoff closure for SoC sub-system partitions, driving RTL-to-GDS execution to achieve first-pass silicon success. Lead PnR execution and closure, converge from synthesis through route, and complete closure signoff on STA, EMIR, and PV. Collaborate across AMD business units, CAD, and central methodology teams globally, analyze feedback/data, and improve flows with automation, dashboards, and best practices.

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FursaFursa
AMD
AMD
23 hours ago

Physical Design Lead with STA

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Job Summary

Own physical design signoff closure for SoC sub-system partitions, driving RTL-to-GDS execution to achieve first-pass silicon success. Lead PnR execution and closure, converge from synthesis through route, and complete closure signoff on STA, EMIR, and PV. Collaborate across AMD business units, CAD, and central methodology teams globally, analyze feedback/data, and improve flows with automation, dashboards, and best practices.
Location: Hyderabad
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Own SS partition PnR execution and closure for SoC sub-system of 10 partitions.
  • •Drive closure convergence from synthesis through route with PnR team members.
  • •Complete closure signoff on STA, EMIR, and PV.
  • •Analyze data and feedback to improve the design team flow and project settings.
  • •Develop automation and dashboarding to refine and improve signoff requirements; collaborate with CAD/methodology and other PPA-equivalent teams across geographies.

Pay and Benefits

Salary: INR 3,338,160 - 4,768,800 annually

Key Requirements

  • •8+ years of physical design signoff closure experience.
  • •Strong PnR background with critical problem-solving to improve PPA and debug.
  • •Technical depth in CTS, route, and STA, plus EMIR-driven power grid knowledge.
  • •Strong skills in SDC coding/debug and PnR/STA signoff correlation/convergence.
  • •Scripting experience (TCL, Perl, Python, Makefile) and ability to deploy/implement ML techniques in physical design.
Experience:8+ years
Education:Bachelor's in computer engineering / electrical engineering
Skills:CollaborationCommunicationSelf-drivingOrganizationAutomation mindset
Tech Stack:RTLGDSSTAEMIRPVCTSSynthesisPlace and routeTiming closurePhysical verificationSDCTCLPerlPythonMakefileSynopsysCadenceMentorMachine learningDashboarding

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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