Senior /Staff AMS Layout engineer-DPG-LPDDR

Micron Technology
Hyderabad
Workplace: OnsiteFull timeFunction: Solutions Engineering & Sales EngineeringExperience: 3-12 yearsSkills: ["Cross-functional collaboration","Problem-solving","Continuous improvement","Mentorship","Layout methodology development"]

Own and drive custom analog and mixed-signal layout for critical LPDDR PHY blocks, from datapath and bias networks to IO front ends and reference circuits. Execute high-speed LPDDR interface layout with signal-integrity focus (skew, impedance matching, shielding, crosstalk, jitter). Lead array-based layout strategies, co-design with circuit teams, and ensure signoff closure through DRC/LVS, parasitic extraction, and simulation correlation—optimizing PPA and manufacturability for first-pass silicon success.

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FursaFursa
Micron Technology
Micron Technology
2 weeks ago

Senior /Staff AMS Layout engineer-DPG-LPDDR

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Last checked: 13 hours agoStatus: Live

Job Summary

Own and drive custom analog and mixed-signal layout for critical LPDDR PHY blocks, from datapath and bias networks to IO front ends and reference circuits. Execute high-speed LPDDR interface layout with signal-integrity focus (skew, impedance matching, shielding, crosstalk, jitter). Lead array-based layout strategies, co-design with circuit teams, and ensure signoff closure through DRC/LVS, parasitic extraction, and simulation correlation—optimizing PPA and manufacturability for first-pass silicon success.
Location: Hyderabad
Workplace: Onsite
Employment Type: Full time
Job Function: Solutions Engineering & Sales Engineering
Seniority: Mid level

Key Responsibilities

  • •Own and drive custom analog and mixed-signal layout for critical LPDDR PHY blocks, ensuring robust operation across PVT with high matching accuracy.
  • •Lead high-speed LPDDR interface layout execution and address signal integrity issues including skew, impedance matching, shielding, crosstalk, and jitter sensitivity.
  • •Architect and implement scalable array-based layout strategies for DQ/DQS byte lanes, CA lanes, and replica paths with strict symmetry and pitch matching.
  • •Drive integration of custom digital and mixed-signal blocks within the PHY while managing clocking, congestion, and isolation of sensitive analog regions.
  • •Ensure physical verification and signoff closure (DRC/LVS, parasitic extraction, simulation correlation) and perform post-layout optimization/ECOs to improve margin, yield, and manufacturability while supporting JEDEC compliance.

Key Requirements

  • •3-12 years of hands-on experience in custom analog and high-speed layout design for critical analog blocks and LPDDR/high-speed interfaces at advanced technology nodes.
  • •Proven expertise in implementing and delivering LPDDR interface and PHY layout with robust operation across PVT, low noise coupling, and high matching accuracy.
  • •Experience solving high-speed signal integrity challenges such as skew control, impedance matching, shielding, crosstalk mitigation, and jitter sensitivity.
  • •Ability to architect and implement scalable array-based layout strategies (DQ/DQS byte lanes, CA lanes, replica paths) with strict symmetry, pitch matching, repeatability, and multi-channel scalability.
  • •Experience driving physical verification and signoff closure including DRC/LVS, parasitic extraction, and simulation correlation.
Experience:3-12 yearsLPDDRAnalog designMixed-signalHigh-speed interfacesSemiconductorSilicon validation
Skills:Cross-functional collaborationProblem-solvingContinuous improvementMentorshipLayout methodology development
Tech Stack:LPDDRLPDDRxSKILLPythonTCLDRCLVSParasitic extractionSimulation correlationJEDECVXLECOPPAIREMTiming closure

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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