R&D Engineer

Broadcom
India
Workplace: OnsiteFull timeFunction: Research & Scientific (R&D)Experience: 4-8 yearsSkills: ["Communication","Collaboration"]

As part of the TLR team, own physical design and verification activities including place-and-route, CTS and routability/congestion analysis, and DRC/LVS checks (plus antenna, LUP, DFM/DFY, ERC and ESD latchup). Integrate analog blocks, meet RC requirements, run post–tapeout integrity checks and eJob view release, and implement timing ECOs and IR-drop fixes (SPEF/GPD extraction, EM/noise analysis). Use Perl/TCL scripting and CAD tools like Cadence Innovus and Calibre, collaborating to hit PD milestones.

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FursaFursa
Broadcom
Broadcom
4 weeks ago

R&D Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 5 hours agoStatus: Live
Reposted: similar role first listed 3 weeks ago

Job Summary

As part of the TLR team, own physical design and verification activities including place-and-route, CTS and routability/congestion analysis, and DRC/LVS checks (plus antenna, LUP, DFM/DFY, ERC and ESD latchup). Integrate analog blocks, meet RC requirements, run post–tapeout integrity checks and eJob view release, and implement timing ECOs and IR-drop fixes (SPEF/GPD extraction, EM/noise analysis). Use Perl/TCL scripting and CAD tools like Cadence Innovus and Calibre, collaborating to hit PD milestones.
Location: India
Workplace: Onsite
Employment Type: Full time
Job Function: Research & Scientific (R&D)
Seniority: Mid level

Key Responsibilities

  • •Perform place and route, CTS and routability/congestion analysis.
  • •Execute physical verification including DRC/LVS and checks for antenna, LUP, DFM/DFY, ERC and ESD latchup through chip finishing and tapeout.
  • •Integrate analog blocks and ensure RC requirements for manual/special signals are met.
  • •Implement timing ECOs, IR drop fixes, SPEF/GPD extraction, signal EM fixes, and noise analysis.
  • •Conduct post-tapeout integrity checks and release eJob view; communicate with team to achieve PD milestones.

Key Requirements

  • •4 to 8 years of relevant experience in physical design/verification activities.
  • •Strong knowledge of DRC/LVS and related checks including antenna, LUP, DFM/DFY, ERC, and ESD latchup.
  • •Hands-on ability to integrate analog blocks and meet RC requirements for manual/special signals.
  • •Good understanding of VLSI fabrication process and cadence Innovus/Calibre CAD tools.
  • •Scripting knowledge in Perl and TCL; ability to implement timing ECOs and IR-drop fixes with supporting extraction and analysis.
Experience:4-8 yearsVLSISemiconductor
Skills:CommunicationCollaboration
Tech Stack:PerlTCLCalibreCadenceInnovusDRCLVSERCDFMDFYCTSSTAPTSISPEFGPDEJob viewIR dropTiming ECOSignal EMNoise analysis

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn