Layout Engineer, DEG

Micron Technology
Boise
Workplace: OnsiteFull timeFunction: Hardware, Embedded & Systems EngineeringSkills: ["Communication","Collaboration"]

Shape block-level layouts for Micron’s DRAM designs, building and optimizing using Cadence Virtuoso. Apply physical constraints (PDN, pin placement, blockages, hierarchy) to meet DRC/LVS, density, and reliability requirements, while supporting parasitic extraction, post-layout verification, and ECO activities. Create partial custom layouts for device-level or small analog blocks and collaborate closely with cross-site teams to drive quality and scalability across generations of memory technology.

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FursaFursa
Micron Technology
Micron Technology
2 months ago

Layout Engineer, DEG

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Last checked: 20 hours agoStatus: Live

Job Summary

Shape block-level layouts for Micron’s DRAM designs, building and optimizing using Cadence Virtuoso. Apply physical constraints (PDN, pin placement, blockages, hierarchy) to meet DRC/LVS, density, and reliability requirements, while supporting parasitic extraction, post-layout verification, and ECO activities. Create partial custom layouts for device-level or small analog blocks and collaborate closely with cross-site teams to drive quality and scalability across generations of memory technology.
Location: Boise
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering

Key Responsibilities

  • •Build block-level layouts in Cadence Virtuoso, including floorplanning, placement, routing, and optimization.
  • •Apply layout methods and physical constraints such as PDN, pin placement, routing blockages, and hierarchy.
  • •Ensure compliance with DRC, LVS, density, and reliability requirements.
  • •Support parasitic extraction, post-layout verification, and ECO activities.
  • •Create partial custom layouts for selected device-level or small analog blocks.

Pay and Benefits

Perks:Health InsuranceDentalVisionPaid LeavePaid Holidays

Key Requirements

  • •Experience performing physical layout using Cadence Virtuoso or similar tools.
  • •Familiarity with DRC, LVS, physical verification, and reliability checks.
  • •Ability to plan, document, and review layout goals with cross-site teams.
  • •Experience with DRAM, memory circuits, or large hierarchical designs.
  • •Hands-on experience with partial custom layout for devices or small analog circuits.
Experience:DRAMSemiconductorsMemory circuits
Skills:CommunicationCollaboration
Tech Stack:Cadence VirtuosoDRCLVSPhysical verificationPDNParasitic extractionECOFloorplanningPlacementRoutingDensityPin placement

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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Glassdoor: 3.7
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