Design Verification Engineer

AMD
Santa Clara, Austin
Workplace: HybridFull timeUSD 145,600 - 249,600 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 6+ yearsSkills: ["Communication","Presentation","Collaboration","Mentoring","Knowledge sharing"]

Drive verification efforts for server memory DDR interfaces, working on DDR5 and DFI memory systems and related protocols such as LPDDR5/LPDDR6. Build and execute verification plans, align firmware/BIOS/software with PHY interactions, and partner across RTL and cross-functional teams for planning and debug. Contribute to verification methodology, share knowledge, and support post-Si performance, power, and functional issue investigation and resolution.

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FursaFursa
AMD
AMD
5 days ago

Design Verification Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 7 hours agoStatus: Live

Job Summary

Drive verification efforts for server memory DDR interfaces, working on DDR5 and DFI memory systems and related protocols such as LPDDR5/LPDDR6. Build and execute verification plans, align firmware/BIOS/software with PHY interactions, and partner across RTL and cross-functional teams for planning and debug. Contribute to verification methodology, share knowledge, and support post-Si performance, power, and functional issue investigation and resolution.
Location: Santa Clara, Austin
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Partner with verification engineers to develop and execute verification plans for DDR5, LPDDR5, and DFI memory systems in server products.
  • •Understand PHY interaction across HW (silicon), FW, BIOS, and SW to ensure alignment and enable memory interface features.
  • •Analyze RTL and micro-architecture to support cross-functional discussions with IP/domain architects and design engineers for planning and debug.
  • •Contribute to verification methodology through knowledge sharing and related improvements.
  • •Support post-Si teams with product performance, power, and functional issue debug and resolution.

Pay and Benefits

Salary: USD 145,600 - 249,600 annually

Key Requirements

  • •Bachelor’s +8 years or Master’s +6 years in a related discipline.
  • •Advanced SystemVerilog and UVM-based testbench, simulation environment, and functional coverage model development for DDR5/LPDDR5 systems.
  • •Strong proficiency in SystemVerilog assertions, constraints, and coverage.
  • •Experience with formal verification methods and tool usage beyond standard applications.
  • •Ability to collaborate across hardware, firmware, and software teams to align system-level memory architecture and define validation requirements early.
Experience:6+ yearsSemiconductor
Skills:CommunicationPresentationCollaborationMentoringKnowledge sharing
Languages:En-us
Tech Stack:SystemVerilogUVMCC++PythonPerlDDR5DFILPDDR5LPDDR6DIMMsRTLBIOSFWSimulationFunctional coverageAssertionsConstraintsGLSNLP

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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