Principal Engineer - Standard Cell Design

Intel
United States
Workplace: HybridFull timeUSD 220,920 - 311,890 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 10+ yearsEducation: phdSkills: ["Communication","Problem-solving","Collaboration","Technical leadership","Data analysis"]

Shape Intel’s standard cell library strategy and drive circuit innovation for high-performance, low-voltage operation across leading-edge process nodes. Lead PPA and Vmin optimization efforts, interface with foundry customers, and collaborate with DTCO, product design teams, and EDA partners to co-optimize scalable library solutions. Mentor circuit designers, define circuit methodology and best practices, and analyze silicon/design data to debug issues and improve next-generation library performance.

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Intel
Intel
1 month ago

Principal Engineer - Standard Cell Design

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Last checked: 8 hours agoStatus: Live
Reposted: similar role first listed 1 month ago

Job Summary

Shape Intel’s standard cell library strategy and drive circuit innovation for high-performance, low-voltage operation across leading-edge process nodes. Lead PPA and Vmin optimization efforts, interface with foundry customers, and collaborate with DTCO, product design teams, and EDA partners to co-optimize scalable library solutions. Mentor circuit designers, define circuit methodology and best practices, and analyze silicon/design data to debug issues and improve next-generation library performance.
Location: United States
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Shape standard cell library strategy including content definition, cell selection, and ecosystem usability.
  • •Drive circuit innovation for high-performance and low-voltage operation, especially sequential and clocking circuits.
  • •Lead PPA and Vmin optimization efforts and balance tradeoffs across performance, power, and area.
  • •Optimize standard cell libraries on Intel leading-edge process nodes and meet internal/external foundry customer needs.
  • •Mentor circuit designers and technical leaders, develop/refine circuit methodology, and analyze silicon/design data to debug and improve results.

Pay and Benefits

Salary: USD 220,920 - 311,890 annually
Equity and Bonus:Equity
Perks:Health InsuranceRetirementPaid Leave

Key Requirements

  • •Ph.D. or Master’s degree with 10+ years of industry experience in foundation IP design, design-technology co-optimization, and advanced semiconductor technology.
  • •Deep understanding of MOSFET electrical characteristics and transistor device physics, layout, and variability at advanced technology nodes.
  • •Working knowledge of transistor-level design for static circuits including latches and flops, and experience with standard cell development.
  • •Understanding of standard cell circuit design tradeoffs across power, performance, area, and Vmin, plus PPA/Vmin and variation impacts.
  • •Experience with standard cell characterization tools and Spice circuit simulations, including identifying/designing/verifying cells to improve product-level PPA.
Experience:10+ yearsSemiconductorsEDAStandard cell designSilicon characterization
Education:PhD / Doctorate
Skills:CommunicationProblem-solvingCollaborationTechnical leadershipData analysis
Tech Stack:SpiceEDADTCOPPAVminMOSFETMOSFET electrical characteristicsStandard cell libraries

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
Glassdoor
Glassdoor: 3.8
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