Principal Engineer - Standard Cell Design

Shape Intel’s standard cell library strategy and drive circuit innovation for high-performance, low-voltage operation across leading-edge process nodes. Lead PPA and Vmin optimization efforts, interface with foundry customers, and collaborate with DTCO, product design teams, and EDA partners to co-optimize scalable library solutions. Mentor circuit designers, define circuit methodology and best practices, and analyze silicon/design data to debug issues and improve next-generation library performance.