Cadence Design Systems

3 weeks ago

Sr Principal Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 6 hours agoStatus: Live

Job Summary

Design and lead complex high-speed interface and memory/IP work, with deep expertise in SerDes, PLLs, clocking, datapaths, and analog I/O design. Bring hands-on experience across PCIe generations and DDR variants, ensuring strong signal and reliability integrity (ESD, SI/PI). Manage cross-functional dependencies, lead complex IP efforts, and mentor junior engineers while communicating clearly and solving hard technical problems.

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Sr. Manager level

Key Responsibilities

•Apply deep knowledge of high-speed SerDes and memory interface circuits (I/O, PLLs, clocking, datapaths).
•Execute hands-on design work for PCIe Gen3/4/5/6 and DDR memory interface circuits (GDDRx/DDRx/LPDDRx).
•Develop strong analog and I/O design with expertise in ESD, reliability, and SI/PI considerations.
•Lead complex IP initiatives and manage cross-functional dependencies.
•Lead and mentor junior engineers; use strong written and verbal communication to solve problems.

Key Requirements

•12-17 years of experience in high-speed SerDes and memory interface circuit design.
•BE/ B Tech/ ME/ M Tech / MS education.
•In-depth understanding of SerDes/Memory interfaces including I/O, PLLs, clocking, and datapaths.
•Hands-on experience with PCIe Gen3/4/5/6 and GDDRx/DDRx/LPDDRx memory interface circuits.
•Strong analog design and I/O fundamentals, including knowledge of ESD, reliability, SI, and PI.

Experience:12-17 yearsElectronic designHardwareIP development

Education:Bachelor's

Skills:LeadershipMentoringCommunicationProblem-solving

Tech Stack:SerDesPLLClockingDatapathPCIeGDDRxDDRxLPDDRxAnalog designESDReliabilitySIPI

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

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Cadence Design Systems

3 weeks ago

Sr Principal Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 6 hours agoStatus: Live

Job Summary

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Sr. Manager level

Key Responsibilities

•Apply deep knowledge of high-speed SerDes and memory interface circuits (I/O, PLLs, clocking, datapaths).
•Execute hands-on design work for PCIe Gen3/4/5/6 and DDR memory interface circuits (GDDRx/DDRx/LPDDRx).
•Develop strong analog and I/O design with expertise in ESD, reliability, and SI/PI considerations.
•Lead complex IP initiatives and manage cross-functional dependencies.
•Lead and mentor junior engineers; use strong written and verbal communication to solve problems.

Key Requirements

•12-17 years of experience in high-speed SerDes and memory interface circuit design.
•BE/ B Tech/ ME/ M Tech / MS education.
•In-depth understanding of SerDes/Memory interfaces including I/O, PLLs, clocking, and datapaths.
•Hands-on experience with PCIe Gen3/4/5/6 and GDDRx/DDRx/LPDDRx memory interface circuits.
•Strong analog design and I/O fundamentals, including knowledge of ESD, reliability, SI, and PI.

Experience:12-17 yearsElectronic designHardwareIP development

Education:Bachelor's

Skills:LeadershipMentoringCommunicationProblem-solving

Tech Stack:SerDesPLLClockingDatapathPCIeGDDRxDDRxLPDDRxAnalog designESDReliabilitySIPI

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor