2 months ago

Senior Physical Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Shape the next generation of custom IP and SoC designs by leading RTL-to-GDS flow, from synthesis to floorplanning, for high-performance computing. Collaborate with architecture and logic teams to optimize power, speed and area, develop reusable physical design methodologies, and automate workflows with scripting across next‑gen process nodes. Contribute to multi-tape-out projects and ensure manufacturability and reliability.

Location: Penang

Workplace: Hybrid

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Execute RTL-to-GDS implementation of custom IP and SoC designs, including synthesis, place-and-route, clock tree synthesis, and floor planning.
•Conduct comprehensive static timing analysis, power and noise analysis, and reliability assessments to meet stringent design specifications.
•Perform verification and signoff, including formal equivalence verification, layout verification, and static and dynamic power integrity checks.
•Identify and resolve design violations, optimizing for parameters such as power, frequency, and area.
•Develop and refine physical design methodologies, leveraging EDA tools to enhance automation and workflow efficiency.

Key Requirements

•Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
•6+ years of experience in the structural/physical design domain (or 4+ years with a Master’s, or 2+ years with a PhD)
•Proficiency in RTL-to-GDS tools and methodologies (synthesis, place-and-route, clock tree synthesis, floor planning)
•Deep expertise in static timing analysis (SDC development, timing budgeting, timing signoff using Primetime)
•Strong scripting skills in Perl, TCL, Python, or Shell to automate workflows and debug issues

Experience:6+ yearsSemiconductorEDAPhysical designSoCIPRTL-to-GDS

Education:Bachelor's

Skills:ScriptingAutomationTeam collaborationProblem-solving

Tech Stack:PerlTCLPythonShellPrimetimeRTLGDSEDA toolsVerilogVHDL

Company Brief

Intel

Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1968

Glassdoor: 3.8

Website LinkedIn Glassdoor

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Intel

2 months ago

Senior Physical Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Location: Penang

Workplace: Hybrid

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Execute RTL-to-GDS implementation of custom IP and SoC designs, including synthesis, place-and-route, clock tree synthesis, and floor planning.
•Conduct comprehensive static timing analysis, power and noise analysis, and reliability assessments to meet stringent design specifications.
•Perform verification and signoff, including formal equivalence verification, layout verification, and static and dynamic power integrity checks.
•Identify and resolve design violations, optimizing for parameters such as power, frequency, and area.
•Develop and refine physical design methodologies, leveraging EDA tools to enhance automation and workflow efficiency.

Key Requirements

•Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
•6+ years of experience in the structural/physical design domain (or 4+ years with a Master’s, or 2+ years with a PhD)
•Proficiency in RTL-to-GDS tools and methodologies (synthesis, place-and-route, clock tree synthesis, floor planning)
•Deep expertise in static timing analysis (SDC development, timing budgeting, timing signoff using Primetime)
•Strong scripting skills in Perl, TCL, Python, or Shell to automate workflows and debug issues

Experience:6+ yearsSemiconductorEDAPhysical designSoCIPRTL-to-GDS

Education:Bachelor's

Skills:ScriptingAutomationTeam collaborationProblem-solving

Tech Stack:PerlTCLPythonShellPrimetimeRTLGDSEDA toolsVerilogVHDL

Company Brief

Intel

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1968

Glassdoor: 3.8

Website LinkedIn Glassdoor