HBM SoC Physical Design Engineer

Micron Technology
United States
Workplace: OnsiteFull timeUSD 121,000 - 205,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 3+ yearsEducation: bachelorsSkills: ["Mentorship","Automation","Problem-solving"]

Drive physical implementation of advanced HBM SoC designs within the Heterogeneous Integration Group, taking projects from netlist to GDSII. Own floor-planning, placement, CTS, routing, and physical optimization to hit PPA targets, while leading timing closure across multi-mode/multi-corner scenarios. Integrate complex IP, run physical signoff (DRC/LVS/IR drop/EM), support tape-out, and improve productivity via scripting and AI-enabled workflows.

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FursaFursa
Micron Technology
Micron Technology
5 days ago

HBM SoC Physical Design Engineer

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Last checked: 10 hours agoStatus: Live

Job Summary

Drive physical implementation of advanced HBM SoC designs within the Heterogeneous Integration Group, taking projects from netlist to GDSII. Own floor-planning, placement, CTS, routing, and physical optimization to hit PPA targets, while leading timing closure across multi-mode/multi-corner scenarios. Integrate complex IP, run physical signoff (DRC/LVS/IR drop/EM), support tape-out, and improve productivity via scripting and AI-enabled workflows.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets.
  • •Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios by partnering with RTL, architecture, and STA/signoff.
  • •Integrate complex IP with focus on robust physical integration and timing/power integrity.
  • •Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, resolving violations efficiently.
  • •Support tape-out execution and post-silicon debug by correlating silicon behavior with PD/STA/power analysis; improve productivity via scripting/automation.

Pay and Benefits

Salary: USD 121,000 - 205,000 annually
Equity and Bonus:Equity
Perks:Paid LeaveHealth InsuranceDentalVisionEquity

Key Requirements

  • •Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs.
  • •Proficiency with industry EDA tools such as Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, or Siemens Calibre.
  • •Solid STA fundamentals, clocking, constraints (SDC), and common closure techniques like buffering and path shaping.
  • •Experience with power intent and power delivery considerations, including UPF/CPF concepts and power grid planning.
  • •Familiarity with physical verification/signoff concepts such as DRC, LVS, ERC, and parasitic extraction awareness.
Experience:3+ yearsSemiconductorsHBMSoC
Education:Bachelor's in electrical engineering
Skills:MentorshipAutomationProblem-solving
Tech Stack:Cadence InnovusCadence TempusSynopsys ICC2PrimeTimeSiemens CalibreSTASDCUPFCPFDRCLVSERCIR dropEMGDSIIMMMCDFTMBIST

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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