Lead Design Engineer

Cadence Design Systems
India
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 4-6 yearsEducation: bachelorsSkills: ["Communication","Analytical","Problem-solving","Team player","Self-motivated"]

Lead physical design engineer responsible for end-to-end physical design tasks including floor planning, power grid design, place-and-route, clock tree synthesis, timing/SI/EM-IR signoff, DFM/DFT verification, and tapeouts. Work with RTL and Analog teams to deliver high-performance, low-power IPs/SoCs across advanced nodes (7nm/5nm/3nm/2nm) using Cadence tools (Genus, Innovus, Tempus, Voltus).

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FursaFursa
Cadence Design Systems
Cadence Design Systems
2 months ago

Lead Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 11 hours agoStatus: Live
Reposted: similar role first listed 8 months ago

Job Summary

Lead physical design engineer responsible for end-to-end physical design tasks including floor planning, power grid design, place-and-route, clock tree synthesis, timing/SI/EM-IR signoff, DFM/DFT verification, and tapeouts. Work with RTL and Analog teams to deliver high-performance, low-power IPs/SoCs across advanced nodes (7nm/5nm/3nm/2nm) using Cadence tools (Genus, Innovus, Tempus, Voltus).
Location: India
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Design responsibility including floor planning, power grid design, place and route, clock tree synthesis, timing/SI closure, power/EM-IR signoff, physical verification (DRC/LVS/Antenna), and DFM Closure
  • •Physical design implementation of Cadence IPs using Genus, Innovus, Tempus, Voltus and other backend tools
  • •Physical design for PPA optimization of high-performance, low-power interface IPs (DDR, LPDDR, PCIE, UCIE) and test chips for 7nm/5nm/3nm/2nm nodes
  • •Work on diverse designs including low power, high-speed, and area-optimized implementations
  • •Collaborate with RTL and Analog teams to ensure on-time tapeouts

Key Requirements

  • •B.Tech/BE/ME/Mtech with 4-6 years hands-on experience in physical design and physical verification
  • •Experience with ASIC design flow, hierarchical physical design strategies, methodologies and deep sub-micron technology issues
  • •Solid knowledge on physical design, static timing analysis, Low Power Design, EM/IR/crosstalk analysis, formal verification, physical verification, DFM, DFT
  • •Successful track records of taping out complex IPs & SoCs at 16/10/7/5/3 nm with different foundries
  • •Power user of Cadence implementation tools, such as Genus, Innovus, Quantus, Tempus, PVS, Voltus; automation with Makefile/Tcl/Tk/Perl/Python
Experience:4-6 yearsSemiconductorASICVLSIEDA
Education:Bachelor's
Skills:CommunicationAnalyticalProblem-solvingTeam playerSelf-motivated
Languages:English
Tech Stack:GenusInnovusTempusVoltusPVSQuantusMakefileTclTkPerlPythonDDRLPDDRPCIECadenceDFMDFTEM-IRDLPLVS

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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