Senior Physical Design Engineer

Own end-to-end physical design implementation for custom IP and SoC designs, executing the RTL-to-GDS flow including synthesis, place and route, timing analysis, and verification. Perform static timing, noise/signal integrity, and power distribution optimization, then drive timing closure by analyzing verification results and recommending fixes. Contribute to physical design methodology and flow automation to improve efficiency and scalability within Intel’s silicon design and manufacturing engineering team.