Physical Design Engineer

AMD
Markham
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Collaboration","Analytical thinking","Attention to detail","Communication","Mentorship"]

Drive best-in-class Performance, Power, and Area (PPA) outcomes for AMD graphics processor IP. Partner with RTL, Physical Design, Methodology, and CAD teams to translate architectures into high-quality silicon, influence decisions early, and resolve timing/frequency and other bottlenecks. Lead PPA improvements across critical graphics blocks, optimize tools and flows, deliver PD tile recipes, and evaluate standard-cell impacts from RTL through GDSII.

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FursaFursa
AMD
AMD
2 days ago

Physical Design Engineer

âś“ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 29 minutes agoStatus: Live
Reposted: similar role first listed 5 months ago

Job Summary

Drive best-in-class Performance, Power, and Area (PPA) outcomes for AMD graphics processor IP. Partner with RTL, Physical Design, Methodology, and CAD teams to translate architectures into high-quality silicon, influence decisions early, and resolve timing/frequency and other bottlenecks. Lead PPA improvements across critical graphics blocks, optimize tools and flows, deliver PD tile recipes, and evaluate standard-cell impacts from RTL through GDSII.
Location: Markham
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Lead engineering efforts to drive PPA improvements for critical graphics blocks and act as the main point of contact between Physical Design and RTL teams.
  • •Study block microarchitecture and data flow to determine optimal memory placement and synthesis/P&R recipes.
  • •Partner with RTL teams to address potential bottlenecks for frequency, LOL, and timing issues early in the project cycle.
  • •Collaborate with methodology and CAD teams to optimize tools/flows to achieve best-in-class PPA.
  • •Deliver best-known recipes to PD tile owners and analyze standard cell library options to evaluate PPA impact.

Key Requirements

  • •Experience in ASIC physical design from RTL to GDSII.
  • •Strong RTL analysis skills including Verilog, timing analysis, and library understanding.
  • •Knowledge of design margining methodology, low voltage design, and silicon–STA correlation.
  • •Hands-on experience taping out 3nm, 5nm, 7nm and/or 16nm SoC.
  • •Working experience with CAD tools such as Synopsys, Cadence, and Mentor Graphics.
Experience:ASIC physical designSoCGraphics processors
Education:Bachelor's in computer engineering/Electrical Engineering
Skills:CollaborationAnalytical thinkingAttention to detailCommunicationMentorship
Tech Stack:VerilogTiming AnalysisSTASynopsysCadenceMentor GraphicsRTLGDSIIP&RStandard cell library

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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