PLL Design Engineer

AMD
United States
Workplace: HybridFull timeUSD 156,100 - 223,000 annuallyFunction: Design (Product/UX/UI/Visual)Education: mastersSkills: ["Quality-oriented mindset","Communication","Team spirit","Analytical/problem solving","Attention to details","Self-starter"]

Define, specify, and implement current and future advanced PLL IPs for AMD products. Design complex PLL building blocks from architecture through transistor-level circuitry, and run pre-tapeout verification to validate performance, power, reliability, and timing. Partner with mask design and post-silicon characterization teams to deliver physical design and test plans, while leading/mentoring junior engineers. Uses Cadence tools and simulation workflows for high-speed analog/mixed-signal designs in FinFET nodes.

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FursaFursa
AMD
AMD
1 day ago

PLL Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 8 hours agoStatus: Live

Job Summary

Define, specify, and implement current and future advanced PLL IPs for AMD products. Design complex PLL building blocks from architecture through transistor-level circuitry, and run pre-tapeout verification to validate performance, power, reliability, and timing. Partner with mask design and post-silicon characterization teams to deliver physical design and test plans, while leading/mentoring junior engineers. Uses Cadence tools and simulation workflows for high-speed analog/mixed-signal designs in FinFET nodes.
Location: United States
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Design complex PLL building blocks, including architecture development and transistor-level circuit design.
  • •Run pre-tapeout verification flows to confirm PLL design meets performance, power, reliability, and timing requirements.
  • •Collaborate with mask design engineers on physical design delivery and define production/bench test plans for post-silicon silicon evaluation.
  • •Work with post-silicon characterization groups to ensure interlocked, high-quality execution.
  • •Lead and mentor junior engineers.

Pay and Benefits

Salary: USD 156,100 - 223,000 annually

Key Requirements

  • •Solid knowledge of mixed-signal circuit design in FinFET technology for PLLs and related subblocks (e.g., VCO, charge pump, dividers, state machines, LDO, bandgap, TDC, interpolator circuits, high-speed buffers).
  • •Solid knowledge of industry-standard tools and practices for analog circuit design, including physical design and STA methodology/scripts (Tcl).
  • •Good knowledge of scripting languages including Perl and Python.
  • •Hands-on design experience in performance analog and hybrid Phase Locked Loops, including ADC/DAC converter data converter, VCO, LDO, bandgap, charge pump, op-amps, and interpolator circuits.
  • •Preferred: Master’s or Ph.D. in electrical engineering (or equivalent).
Experience:Semiconductor industryMixed-signal circuit designFinFETPLL designAnalog designPost-silicon characterization
Education:Master's in Electrical engineering
Skills:Quality-oriented mindsetCommunicationTeam spiritAnalytical/problem solvingAttention to detailsSelf-starter
Tech Stack:FinFETCadence ADE-LCadence ADE-XLTclPerlPythonSpectreHspiceAFSMATLABSystem VerilogCadence custom circuit designMonte-Carlo simulationsNoise simulationsAging simulationsEM simulationsIR drop simulationsStability analysisDRCLVS

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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