FPGA Design Verification and validation Engineer

AMD
Hyderabad
Workplace: OnsiteFull timeINR 3,338,160 - 4,768,800 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 6+ yearsEducation: bachelorsSkills: ["Communication","Collaboration","Debugging","Organizational skills","Teamwork"]

Own end-to-end processing system solution planning and execution for AMD/Xilinx FPGA-based products, including Vivado IP configuration through software execution for customer use cases. Collaborate with marketing, architects, hardware, pre/post-silicon verification, and firmware teams to define specifications, scope, and timelines. Build processing IP solutions for AMD AECG FPGA/SoC/ACAP targets across bare-metal and OS-hosted environments, and debug systems on boards.

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FursaFursa
AMD
AMD
1 week ago

FPGA Design Verification and validation Engineer

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Last checked: 5 hours agoStatus: Live

Job Summary

Own end-to-end processing system solution planning and execution for AMD/Xilinx FPGA-based products, including Vivado IP configuration through software execution for customer use cases. Collaborate with marketing, architects, hardware, pre/post-silicon verification, and firmware teams to define specifications, scope, and timelines. Build processing IP solutions for AMD AECG FPGA/SoC/ACAP targets across bare-metal and OS-hosted environments, and debug systems on boards.
Location: Hyderabad
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Plan and execute end-to-end processing system solution, from Vivado IP configuration through software execution for customer use cases.
  • •Collaborate with marketing, architects, hardware, pre/post silicon verification, and firmware teams to define processing system specifications and implementation requirements with scope and timelines.
  • •Drive requirements and deliverables with your team and cross-site stakeholders.
  • •Develop processing IP solutions targeting AMD AECG FPGA/SoC/ACAP systems, including bare-metal and OS-hosted environments.
  • •Debug and troubleshoot processing systems on boards using debugger/scopes and support hardware/software project execution across all stages.

Pay and Benefits

Salary: INR 3,338,160 - 4,768,800 annually

Key Requirements

  • •6+ years of experience in IP/sub-system/system development and validation with an M.S/M.Tech or B.E/B.S/B.Tech in EE/ECE/CSE.
  • •Proficiency in Verilog/SystemVerilog coding and simulation using tools such as Xilinx simulator, ModelSim, NC-Verilog, and VCS.
  • •Strong FPGA fundamentals including FPGA tool flow, timing constraints, STA, and timing closure.
  • •Knowledge of system-level architecture and interfaces such as AXI, memory controllers, high-speed serial connectivity, PCIe, and Ethernet.
  • •Ability to debug system designs on boards using debugger/scopes and drive hardware/software solution projects end-to-end.
Experience:6+ years
Education:Bachelor's in EE/ECE/CSE
Skills:CommunicationCollaborationDebuggingOrganizational skillsTeamwork
Tech Stack:Vivado IPVivadoVerilogSystemVerilogXilinx simulatorModelSimNC-VerilogVCSAXIPCIeEthernetSDXTclPythonPerlC-ShellCAssemblyEmbedded applications programmingGT transceivers

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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