Senior Asic Design - Cisco Silicon One

Work on Cisco Silicon One Front-End Design, covering the full lifecycle of chip development from micro-architecture specification through RTL implementation, integration, and timing analysis. Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power targets, collaborate with verification engineers to reach coverage closure, and partner with physical design on timing and PnR issues. Perform lab debug, root-cause analysis, and post-silicon validation to support silicon success.