6 months ago

Lead C++ Software Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 4 hours agoStatus: Live

Job Summary

We are seeking a Lead C++ Software Engineer to join the Protium FPGA-Based Prototyping team, developing and optimizing QoR and performance for the Protium Compiler in a small, high-achievement group. You will implement new algorithms in C/C++ for the FPGA platform, contribute to EDA automation, and author design specs and unit tests to advance the next-generation verification product used by top CPU/GPU/HyperScaler teams.

Location: San Jose

Workplace: Onsite

Employment Type: Full time

Job Function: Software Engineering

Seniority: Manager level

Key Responsibilities

•Implement new algorithms and enhancements in C/C++-based code to implement the software stack for the FPGA-based platform with a focus on synthesis/technology mapping.
•Develop the EDA automation flow for the platform with other engineers.
•Write design specifications and unit tests for your code.
•Collaborate with a small team of engineers to improve QoR and performance for the Protium Compiler.
•Contribute to the development of the next-generation FPGA-based verification platform.

Pay and Benefits

Salary: USD 110,600 - 205,400 annually

Perks:Health InsuranceDentalVision401kEquityPaid Leave

Key Requirements

•Bachelor’s in Computer Science, Electrical/Computer Engineering and a minimum of 4 years of related experience, or Master’s and a minimum of 2 years of related experience, or PhD with thesis in a relevant area.
•Ideally you are a solid contributor in the FPGA or ASIC prototyping/synthesis/verification space and have delivered great QoR on these platforms.
•Strong programming skills in C/C++ with clear documentation and the ability to discuss your work with the team.
•Very comfortable with Verilog or SystemVerilog and an understanding of digital circuits.
•Experience with multi-threaded/concurrent programming and familiarity with popular logic simulators; OO programming is a good match; ML/AI algorithms deployment is a plus.

Experience:4+ yearsFPGA prototypingASICEDAQoRC/C++SystemVerilogVerilogMulti-threaded

Education:Bachelor's

Skills:C++VerilogSystemVerilogOO programmingMulti-threaded programming

Languages:English

Tech Stack:C++VerilogSystemVerilogFPGAASICEDAQoR

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

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Cadence Design Systems

6 months ago

Lead C++ Software Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 4 hours agoStatus: Live

Job Summary

Location: San Jose

Workplace: Onsite

Employment Type: Full time

Job Function: Software Engineering

Seniority: Manager level

Key Responsibilities

•Implement new algorithms and enhancements in C/C++-based code to implement the software stack for the FPGA-based platform with a focus on synthesis/technology mapping.
•Develop the EDA automation flow for the platform with other engineers.
•Write design specifications and unit tests for your code.
•Collaborate with a small team of engineers to improve QoR and performance for the Protium Compiler.
•Contribute to the development of the next-generation FPGA-based verification platform.

Pay and Benefits

Salary: USD 110,600 - 205,400 annually

Perks:Health InsuranceDentalVision401kEquityPaid Leave

Key Requirements

•Bachelor’s in Computer Science, Electrical/Computer Engineering and a minimum of 4 years of related experience, or Master’s and a minimum of 2 years of related experience, or PhD with thesis in a relevant area.
•Ideally you are a solid contributor in the FPGA or ASIC prototyping/synthesis/verification space and have delivered great QoR on these platforms.
•Strong programming skills in C/C++ with clear documentation and the ability to discuss your work with the team.
•Very comfortable with Verilog or SystemVerilog and an understanding of digital circuits.
•Experience with multi-threaded/concurrent programming and familiarity with popular logic simulators; OO programming is a good match; ML/AI algorithms deployment is a plus.

Experience:4+ yearsFPGA prototypingASICEDAQoRC/C++SystemVerilogVerilogMulti-threaded

Education:Bachelor's

Skills:C++VerilogSystemVerilogOO programmingMulti-threaded programming

Languages:English

Tech Stack:C++VerilogSystemVerilogFPGAASICEDAQoR

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor