Intel

22 hours ago

Mixed Signal Logic Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 22 hours agoStatus: Live

Job Summary

Own and deliver logic design for mixed-signal DDRPHY IPs within the Memory PHY Group. Define architecture and microarchitecture, implement RTL in SystemVerilog, and set up automation flows for IP logic design. Ensure RTL quality using front-end checks (lint/CDC/RDC/voltage-domain crossings, synthesis QA) and create FE packages for IP milestones. Contribute to automating front-end tool flows and improve timing, coverage closure, robustness, turnaround time, and IP area/power metrics.

Location: Bengaluru

Workplace: Hybrid

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Define architecture and microarchitecture features for the blocks being designed.
•Implement RTL in SystemVerilog and set up automation flows for IP logic design.
•Ensure RTL quality using front-end tools for lint, CDC, RDC, voltage-domain crossings, and synthesis QA checks.
•Create FE packages for IP milestones that meet SoC collateral requirements.
•Drive improvements to coverage closure, timing convergence, turnaround time, robustness, and IP area/power metrics; make critical technical decisions and contribute to RTL delivery automation to validation/backend/SoC teams.

Key Requirements

•10+ years of relevant industry experience with BS/MS degree.
•Proficiency in RTL design and coding using SystemVerilog and Verilog.
•Expertise in mixed-signal fundamentals and low-power design using UPF and clock gating.
•Deep understanding of digital and analog design principles, including clock domain crossing and power-performance tradeoffs.
•Experience with hardware simulation tools (VCS/Verdi) and front-end design tools for lint, CDC, RDC, voltage domain crossings, synthesis, and low-power design.

Experience:10+ years

Skills:CommunicationCross-functional collaborationProblem-solvingDisciplined executionProactive mindset

Tech Stack:SystemVerilogVerilogUPFClock gatingVCSVerdiRTLLintCDCRDCSynthesisFront End design toolsSoC collateralRTL qualityCoverage closureTiming convergenceVSCodeGitHub CopilotFormal Property VerificationGit

Company Brief

Intel

Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1968

Glassdoor: 3.8

Website LinkedIn Glassdoor

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Intel

22 hours ago

Mixed Signal Logic Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 22 hours agoStatus: Live

Job Summary

Location: Bengaluru

Workplace: Hybrid

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Define architecture and microarchitecture features for the blocks being designed.
•Implement RTL in SystemVerilog and set up automation flows for IP logic design.
•Ensure RTL quality using front-end tools for lint, CDC, RDC, voltage-domain crossings, and synthesis QA checks.
•Create FE packages for IP milestones that meet SoC collateral requirements.
•Drive improvements to coverage closure, timing convergence, turnaround time, robustness, and IP area/power metrics; make critical technical decisions and contribute to RTL delivery automation to validation/backend/SoC teams.

Key Requirements

•10+ years of relevant industry experience with BS/MS degree.
•Proficiency in RTL design and coding using SystemVerilog and Verilog.
•Expertise in mixed-signal fundamentals and low-power design using UPF and clock gating.
•Deep understanding of digital and analog design principles, including clock domain crossing and power-performance tradeoffs.
•Experience with hardware simulation tools (VCS/Verdi) and front-end design tools for lint, CDC, RDC, voltage domain crossings, synthesis, and low-power design.

Experience:10+ years

Skills:CommunicationCross-functional collaborationProblem-solvingDisciplined executionProactive mindset

Company Brief

Intel

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1968

Glassdoor: 3.8

Website LinkedIn Glassdoor