Sr Principal Product Engineer

Cadence Design Systems
Bengaluru
Workplace: OnsiteFull timeFunction: Communications, PR & CommunityExperience: 12+ yearsEducation: bachelorsSkills: ["SystemVerilog","UVM","C++","Python","Embedded systems","Verifications methodologies","AI-assisted verification"]

Senior product engineer focused on deploying Portable Stimulus in large SoC verification environments, debugging complex generation and solver issues, and collaborating with Cadence R&D to evolve Perspec and scalable system-level verification methodologies for advanced semiconductor projects.

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Cadence Design Systems
Cadence Design Systems
4 months ago

Sr Principal Product Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 4 hours agoStatus: Live
Reposted: similar role first listed 5 months ago

Job Summary

Senior product engineer focused on deploying Portable Stimulus in large SoC verification environments, debugging complex generation and solver issues, and collaborating with Cadence R&D to evolve Perspec and scalable system-level verification methodologies for advanced semiconductor projects.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Communications, PR & Community

Key Responsibilities

  • •Work directly with semiconductor design and verification teams to deploy Portable Stimulus methodologies in complex SoC programs.
  • •Help debug difficult generation and solver issues involving constraints, resources, execution ordering, and scenario realization.
  • •Investigate real-world modeling challenges that arise in large system-level PSS environments.
  • •Collaborate closely with Cadence R&D to diagnose tool issues, influence new features, and improve PSS standard.
  • •Help define and refine methodologies for scalable system-level verification.

Key Requirements

  • •12+ years of experience in SoC verification, validation, or verification methodology.
  • •Strong hands-on experience with SystemVerilog and UVM or embedded/bare-metal environments.
  • •Solid understanding of constrained-random verification and system-level test generation.
  • •Experience debugging complex verification environments.
  • •Strong programming or scripting skills (C/C++/Python or similar).
Experience:12+ yearsSemiconductorSoC verificationEDAVerification methodology
Education:Bachelor's in Electrical/Computer Engineering
Skills:SystemVerilogUVMC++PythonEmbedded systemsVerifications methodologiesAI-assisted verification
Languages:English
Tech Stack:SystemVerilogUVMC++PythonPerspecPortable StimulusEmulationVirtual platformsPCIeDDRARM

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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