Senior Digital Design Verification Engineer

Texas Instruments
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: ["Collaboration","Interpersonal skills","Communication","Analytical skills","Problem-solving"]

Confirm the accuracy of analog and mixed-signal hardware designs by developing verification strategies, detailed test plans, and chip-top testbenches. Build UVM environments, execute RTL and gate-level simulations with regressions, and drive functional and code coverage closure. Use SystemVerilog Assertions, support protocol verification (I2C, SPI, UART), and perform advanced debugging. Collaborate on post-silicon ATE pattern generation and silicon characterization for product readiness.

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FursaFursa
Texas Instruments
Texas Instruments
1 day ago

Senior Digital Design Verification Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 7 hours agoStatus: Live

Job Summary

Confirm the accuracy of analog and mixed-signal hardware designs by developing verification strategies, detailed test plans, and chip-top testbenches. Build UVM environments, execute RTL and gate-level simulations with regressions, and drive functional and code coverage closure. Use SystemVerilog Assertions, support protocol verification (I2C, SPI, UART), and perform advanced debugging. Collaborate on post-silicon ATE pattern generation and silicon characterization for product readiness.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Drive verification strategy by creating detailed test plans, test cases, and checkers, and developing comprehensive chip-top testbenches.
  • •Develop UVM environments end-to-end, including agents, drivers, monitors, and scoreboards.
  • •Execute RTL and gate-level simulations, run regressions, and track coverage closure across block, expression, toggle, and FSM metrics.
  • •Resolve complex design and testbench issues using advanced debugging and problem-solving techniques.
  • •Collaborate with product and application engineering to support ATE functional pattern generation and silicon characterization.

Key Requirements

  • •Bachelor’s or Master’s degree in electrical engineering (or equivalent experience) in designing equipment, components, or circuitry.
  • •Minimum 5 years of experience in design verification and verification engineering.
  • •Expertise in SystemVerilog (SV) and UVM methodologies, including building verification environments.
  • •Proficiency with Cadence verification tools such as Xcelium, vManager, and JasperGold.
  • •Experience with formal verification (FPV) and CDC/RDC assertions, including low power verification with UPF.
Experience:5+ yearsSemiconductorsHardware verificationAnalog mixed-signalEDA tools
Education:Bachelor's
Skills:CollaborationInterpersonal skillsCommunicationAnalytical skillsProblem-solving
Languages:English
Tech Stack:SystemVerilogUVMCadenceXceliumVManagerJasperGoldRTL simulationGate-Level SimulationUVM environmentsSVAsI2CASISPIUARTFunctional coverageCode coverageFormal Property Verification (FPV)UNR analysisCDCRDC

Company Brief

Texas Instruments
Designs and manufactures semiconductors and analog chips used in industrial, automotive, personal electronics, communications, and enterprise systems. It is one of the world’s largest semiconductor companies, with a broad portfolio of embedded processing and power products.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Dallas, United States
Founded: 1930
WebsiteLinkedIn