Staff Physical Design Engineer, HBM

Micron Technology
Texas
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 7+ yearsEducation: bachelorsSkills: ["Problem-solving","Debugging","Cross-functional communication","Collaboration","Methodology improvement"]

Drive digital physical design implementation for advanced HBM memory products, owning the RTL-to-GDSII flow from floorplanning and placement through CTS, routing, and physical signoff. Lead timing closure across modes/corners, troubleshoot congestion, IR drop, EM, and power integrity, and develop power/clock strategies and low-power implementation (UPF/CPF, power gating). Partner with RTL, DFT, CAD, and verification teams, using scripting/automation to improve methodology and productivity.

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FursaFursa
Micron Technology
Micron Technology
1 week ago

Staff Physical Design Engineer, HBM

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Last checked: 5 hours agoStatus: Live

Job Summary

Drive digital physical design implementation for advanced HBM memory products, owning the RTL-to-GDSII flow from floorplanning and placement through CTS, routing, and physical signoff. Lead timing closure across modes/corners, troubleshoot congestion, IR drop, EM, and power integrity, and develop power/clock strategies and low-power implementation (UPF/CPF, power gating). Partner with RTL, DFT, CAD, and verification teams, using scripting/automation to improve methodology and productivity.
Location: Texas
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Own physical design implementation from synthesized netlist through GDSII, including floorplanning, placement, clock tree synthesis, routing, and physical signoff.
  • •Perform and drive timing closure across multiple modes, corners, and scenarios using STA tools.
  • •Analyze and resolve congestion and timing and power integrity issues including IR drop and EM.
  • •Develop and refine floorplans, power grids, and clocking strategies for high-performance designs, including low-power implementation (UPF/CPF-based power intent and power domains).
  • •Execute physical verification (DRC/LVS/ANT/DFM) and support signoff flows, driving functional and timing ECOs as needed.

Pay and Benefits

Perks:Health InsuranceDentalVisionPaid LeavePaid Holidays

Key Requirements

  • •Strong understanding of the RTL-to-GDSII physical design flow (floorplanning, place & route, clock distribution, timing analysis and closure) using standard EDA tools.
  • •7+ years of experience in a related field and experience with full-chip integration, partitioning, and budgeting.
  • •Strong understanding of power, performance, and area (PPA) tradeoffs and knowledge of low-power architectures (DVFS, power gating, multi-voltage designs).
  • •Proficiency in scripting/programming (TCL, Python, Perl, and/or Shell scripting) and ability to debug complex physical design issues.
  • •Ability to perform and validate Power Distribution Network (PDN) analysis and troubleshoot IR/EM and related power integrity problems.
Experience:7+ yearsSemiconductorsHBMDigital designEDA
Education:Bachelor's in Electrical Engineering
Skills:Problem-solvingDebuggingCross-functional communicationCollaborationMethodology improvement
Tech Stack:HBMRTLGDSIIFloorplanningPlace & routeClock tree synthesisRoutingSTATiming closureDRCLVSANTDFMDFTCADPDNIR dropEMPower integrityPower grid

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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