Physical Design Engineer (Silicon Engineering)

SpaceX
Austin, Irvine, Palo Alto
Workplace: OnsiteFull timeUSD 135,000 - 210,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 1+ yearsEducation: bachelorsSkills: ["Motivated","Proactive","Intellectually curious","Self-driven","Can-do attitude"]

Develop next-generation ASICs for Starlink’s space and ground infrastructure by performing partition synthesis and physical implementation (floorplanning, place & route, signoff). Improve physical design methodologies and automation scripts, collaborate with ASIC design teams on feasibility and timing/power/area targets, and resolve congestion/timing issues. Run and debug signoff closure in STA, noise, physical verification, electromigration, and voltage drop to deliver reliable connectivity hardware.

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FursaFursa
SpaceX
SpaceX
4 hours ago

Physical Design Engineer (Silicon Engineering)

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Job Summary

Develop next-generation ASICs for Starlink’s space and ground infrastructure by performing partition synthesis and physical implementation (floorplanning, place & route, signoff). Improve physical design methodologies and automation scripts, collaborate with ASIC design teams on feasibility and timing/power/area targets, and resolve congestion/timing issues. Run and debug signoff closure in STA, noise, physical verification, electromigration, and voltage drop to deliver reliable connectivity hardware.
Location: Austin, Irvine, Palo Alto
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Entry level

Key Responsibilities

  • •Perform partition synthesis and physical implementation steps including synthesis, floorplanning, place and route, timing, noise, physical verification, electromigration, voltage drop, and signoff checks.
  • •Develop and improve physical design methodologies and automation scripts for various implementation steps.
  • •Collaborate with the ASIC design team on architectural feasibility studies, timing/power/area targets, and RTL/design tradeoffs.
  • •Resolve design/timing/congestion and flow issues by identifying potential solutions and driving execution.
  • •Run, debug, and fix signoff closure issues in STA, noise, logic equivalency, physical verification, electromigration, and voltage drop.

Pay and Benefits

Salary: USD 135,000 - 210,000 annually
Equity and Bonus:Equity
Perks:MedicalVisionDental401kLife InsurancePaid ParentalDisability InsurancePaid LeaveEquity

Key Requirements

  • •Bachelor’s degree in electrical engineering, computer engineering, or computer science.
  • •1+ years of professional experience working on RTL2GDSII physical design and/or physical design flow development.
  • •Experience with industry standard EDA tools, including understanding capabilities and underlying algorithms.
  • •Knowledge of deep sub-micron FinFET and CMOS solid state physics and CMOS digital design principles.
  • •Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.).
Experience:1+ yearsASICEDASemiconductors
Education:Bachelor's
Skills:MotivatedProactiveIntellectually curiousSelf-drivenCan-do attitude
Tech Stack:ASICRTL2GDSIIPhysical designSynthesisFloorplanningPower/ground grid generationPlace and routeTimingNoisePhysical verificationElectromigrationVoltage dropLogic equivalencyStatic timing analysis (STA)DFTScanMBISTLBISTFinFETCMOS

Eligibility

Nationality:US National

Company Brief

SpaceX
Designs, manufactures, and launches advanced rockets and spacecraft for commercial and government customers, aiming to reduce space transportation costs and enable human life on Mars through reusable launch vehicles and integrated space systems.
Industry: Aerospace Manufacturing
Company Size: Enterprise (1,001+ employees)
Growth: Established Company
Valuation: Hectocorn (USD 100B+)
Funding: Series E+
Headquarters: Hawthorne, United States
Founded: 2002
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