ByteDance

5 days ago

ASIC Design Engineer (Video Silicon IP) - Multimedia Lab

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 23 hours agoStatus: Live

Job Summary

Design and implement ASIC hardware for multi-standard video encoding and processing within ByteDance’s Video Silicon IP team. Collaborate with architecture, algorithm, and verification experts to meet area, power, and performance targets, translate codec specifications into hardware micro-architectures, and build RTL for codec pipeline stages. Drive RTL functional correctness with UVM test benches, debug coverage gaps, and support synthesis, timing analysis, and CDC/RDC and physical-design timing closure guidance.

Location: San Jose

Workplace: Onsite

Employment Type: Full time

Job Function: Creative Production (Video/Audio/Photo)

Seniority: Mid level

Key Responsibilities

•Work with architecture, algorithm, and verification teams to build high performance, low power video processing IPs.
•Apply computer architecture and ASIC design knowledge to design hardware for compressing and processing still images and videos.
•Develop micro-architectures to meet stringent area, power, and performance (PPA) targets for multi-standard codec cores.
•Design and implement RTL (SystemVerilog/Verilog) for video codec pipeline stages such as intra/inter prediction, transform & quantization, entropy coding (CABAC/ANS), and in-loop filters.
•Drive RTL functional correctness with directed and constrained-random UVM test benches, debug coverage metrics, and support synthesis, timing analysis, and CDC/RDC checks with physical design guidance.

Key Requirements

•M.S./Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
•2 years of ASIC front-end design experience as a primary RTL owner.
•Proficiency in SystemVerilog RTL design and/or High level Synthesis (HLS).
•Familiarity with UVM/DPI/C++.
•Solid VLSI fundamentals including pipelining, clock gating, memory architecture, bus interfaces (AXI/APB), and SV assertion basics.

Experience:2+ yearsASIC front-end designVideo codecFPGA prototypingImage/video compressionPre-silicon validation

Education:Master's

Skills:CollaborationTechnical excellenceDebuggingAttention to detailProblem-solving

Tech Stack:ASICFPGAVideo codecSystemVerilogVerilogRTLUVMDPIC++HLSVLSIPipeliningClock gatingMemory architectureAXIAPBSV assertionsPythonEDARTL coverage

Company Brief

ByteDance

Develops consumer internet and content platforms, including TikTok and other apps for short-form video, news, and entertainment. It also builds advertising, commerce, and creator tools that connect audiences, brands, and publishers across global markets.

Industry: Digital Media

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Established Company

Headquarters: Beijing, China

Founded: 2012

Website LinkedIn

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ByteDance

5 days ago

ASIC Design Engineer (Video Silicon IP) - Multimedia Lab

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 23 hours agoStatus: Live

Job Summary

Location: San Jose

Workplace: Onsite

Employment Type: Full time

Job Function: Creative Production (Video/Audio/Photo)

Seniority: Mid level

Key Responsibilities

•Work with architecture, algorithm, and verification teams to build high performance, low power video processing IPs.
•Apply computer architecture and ASIC design knowledge to design hardware for compressing and processing still images and videos.
•Develop micro-architectures to meet stringent area, power, and performance (PPA) targets for multi-standard codec cores.
•Design and implement RTL (SystemVerilog/Verilog) for video codec pipeline stages such as intra/inter prediction, transform & quantization, entropy coding (CABAC/ANS), and in-loop filters.
•Drive RTL functional correctness with directed and constrained-random UVM test benches, debug coverage metrics, and support synthesis, timing analysis, and CDC/RDC checks with physical design guidance.

Key Requirements

•M.S./Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
•2 years of ASIC front-end design experience as a primary RTL owner.
•Proficiency in SystemVerilog RTL design and/or High level Synthesis (HLS).
•Familiarity with UVM/DPI/C++.
•Solid VLSI fundamentals including pipelining, clock gating, memory architecture, bus interfaces (AXI/APB), and SV assertion basics.

Experience:2+ yearsASIC front-end designVideo codecFPGA prototypingImage/video compressionPre-silicon validation

Education:Master's

Skills:CollaborationTechnical excellenceDebuggingAttention to detailProblem-solving

Tech Stack:ASICFPGAVideo codecSystemVerilogVerilogRTLUVMDPIC++HLSVLSIPipeliningClock gatingMemory architectureAXIAPBSV assertionsPythonEDARTL coverage

Company Brief

ByteDance

Industry: Digital Media

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Established Company

Headquarters: Beijing, China

Founded: 2012

Website LinkedIn