Senior Staff SOC DFX RTL Design Engineer

AMD
Penang
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Education: mastersSkills: ["Communication","Analytical thinking","Problem-solving","Collaboration","Teamwork"]

Design and integrate DFX features for next-generation microprocessors in AMD’s Radeon Technologies Group Client SOC DFX team. Partner with architecture, IP, and physical design groups to plan, implement, and verify DFX (JTAG, scan, boundary scan, debug, and related techniques). Support first-silicon bring-up with DFT RTL integration, insertion, synthesis, equivalency checking, timing analysis, and production pattern debug and failure analysis.

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FursaFursa
AMD
AMD
2 days ago

Senior Staff SOC DFX RTL Design Engineer

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Last checked: 3 hours agoStatus: Live

Job Summary

Design and integrate DFX features for next-generation microprocessors in AMD’s Radeon Technologies Group Client SOC DFX team. Partner with architecture, IP, and physical design groups to plan, implement, and verify DFX (JTAG, scan, boundary scan, debug, and related techniques). Support first-silicon bring-up with DFT RTL integration, insertion, synthesis, equivalency checking, timing analysis, and production pattern debug and failure analysis.
Location: Penang
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Plan and implement DFX features such as JTAG, scan, boundary scan, and debug features.
  • •Work with CAD and IP teams for requirements and implement DFX features across power scenarios.
  • •Collaborate with the DFX verification team to ensure DFX quality.
  • •Participate in DFX initiatives and process development and provide technical support to cross-functional teams.
  • •Support first-silicon bring-up by performing DFT RTL design integration, insertion, synthesis, equivalency checking, timing analysis, and RTL/netlist DFT verification, including pattern debug support and failure analysis.

Key Requirements

  • •DFT/DFx knowledge including DFT techniques such as JTAG/IEEE standards, scan, ATPG, and memory BIST/repair or logic BIST.
  • •Experience debugging RTL and gate-level simulations using Verilog simulator tools and waveform debugging.
  • •Hands-on DFX implementation and RTL/netlist work including insertion, synthesis, equivalency checking, timing analysis, and constraint definition.
  • •Familiarity with tools and methodologies such as Mentor testkompress and/or Synopsys Tetramax/DFTMAX, plus VCS simulation.
  • •Programming/scripting proficiency with Verilog/SystemVerilog and languages such as Verilog plus C/C++, Python, Perl, and TCL.
Experience:Microprocessors
Education:Master's in computer engineering/Electrical Engineering
Skills:CommunicationAnalytical thinkingProblem-solvingCollaborationTeamwork
Languages:English
Tech Stack:JTAGIEEEDFTDFxScanBoundary ScanATPGMBISTMemory BISTLogic BISTVerilogSystemVerilogVCSMentor testkompressSynopsys TetramaxDFTMAXPerlShell scriptingTCLCAD

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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