Analog Circuit Design Engineer

Intel
Bengaluru
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Experience: 5-9 yearsEducation: bachelorsSkills: ["Technical leadership","Communication","Stakeholder management","Cross-functional collaboration","Structured problem-solving"]

Design and develop advanced analog and mixed-signal circuits for high-speed Intel connectivity, owning critical IP blocks from concept through silicon validation. Lead transistor-level design, simulation, and verification across PVT corners for TX/RX interfaces, SerDes building blocks, PLL/DLL/CDR and clocking circuits, and power/ESD elements. Drive performance closure, collaborate with physical design and cross-functional teams, and support silicon bring-up and root-cause analysis.

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Intel
Intel
2 days ago

Analog Circuit Design Engineer

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Job Summary

Design and develop advanced analog and mixed-signal circuits for high-speed Intel connectivity, owning critical IP blocks from concept through silicon validation. Lead transistor-level design, simulation, and verification across PVT corners for TX/RX interfaces, SerDes building blocks, PLL/DLL/CDR and clocking circuits, and power/ESD elements. Drive performance closure, collaborate with physical design and cross-functional teams, and support silicon bring-up and root-cause analysis.
Location: Bengaluru
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Lead the design, analysis, and optimization of analog and mixed-signal circuits for high-speed IO interfaces.
  • •Develop architecture and circuit implementations for high-speed TX/RX, SerDes building blocks, PLLs/DLLs/CDRs/clocking circuits, equalization/signal conditioning, and power/ESD circuitry.
  • •Perform detailed transistor-level design, simulation, and verification across multiple PVT corners, driving design closure on performance metrics (bandwidth, jitter, noise, power, area, yield, reliability).
  • •Collaborate with physical design teams on layout reviews and post-lay out optimization, and support silicon bring-up, characterization, and correlation between simulation and silicon measurements.
  • •Mentor junior engineers and lead technical reviews to solve complex design challenges across architecture, digital design, signal integrity, package, product engineering, and validation teams.

Key Requirements

  • •Bachelor's or master's degree in electrical engineering, electronics engineering, VLSI, microelectronics, or related fields.
  • •5 to 9 years of industry experience in analog/mixed-signal IC design.
  • •Strong CMOS analog circuit design fundamentals and experience designing high-speed analog circuits in advanced technology nodes.
  • •Hands-on experience with SerDes architectures and/or high-speed IO interfaces, including PLL/DLL/CDR, TX/RX analog front-end, clock distribution, reference/bias circuits, and LDOs.
  • •Expertise in transistor-level design, simulation, and verification (e.g., Cadence Virtuoso, Spectre) plus corner/Monte Carlo/statistical and post-layout verification/debugging.
Experience:5-9 yearsAnalog/mixed-signal IC designHigh-speed IOSilicon debugAdvanced process technologies
Education:Bachelor's in Electrical engineering, Electronics Engineering, VLSI, Microelectronics
Skills:Technical leadershipCommunicationStakeholder managementCross-functional collaborationStructured problem-solving
Tech Stack:Cadence VirtuosoSpectrePythonPerlTCLSKILLSerDesTXRXPLLDLLCDRClock distribution networksBandgap referencesBias generationLDOsPower management circuitsESD protectionPCI Express (PCIe)DDR Memory Interfaces

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
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