DFT ASIC Engineering Technical Leader | ATPG | 10 to 14 years | Bangalore

Cisco
Bengaluru
Workplace: HybridFull timeFunction: Hardware, Embedded & Systems EngineeringExperience: 10-14 yearsEducation: mastersSkills: ["Mentorship","Communication","Project planning","Root-cause analysis","Stakeholder management"]

Lead and mentor a DFT engineering team for Cisco Silicon One, driving innovative design-for-test features from pre-silicon planning through post-silicon debug and production qualification. Own DFT strategy across multiple projects by partnering with chip architects, design, and verification teams. Supervise ATPG, scan compression, memory BIST, and other DFT techniques to improve test coverage and efficiency, while guiding root-cause analysis to enhance yield and reliability.

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Cisco
Cisco
2 days ago

DFT ASIC Engineering Technical Leader | ATPG | 10 to 14 years | Bangalore

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Job Summary

Lead and mentor a DFT engineering team for Cisco Silicon One, driving innovative design-for-test features from pre-silicon planning through post-silicon debug and production qualification. Own DFT strategy across multiple projects by partnering with chip architects, design, and verification teams. Supervise ATPG, scan compression, memory BIST, and other DFT techniques to improve test coverage and efficiency, while guiding root-cause analysis to enhance yield and reliability.
Location: Bengaluru
Workplace: Hybrid
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Manager level

Key Responsibilities

  • •Lead, mentor, and develop a team of DFT engineers responsible for designing and implementing DFT features.
  • •Drive DFT execution across the full product lifecycle from pre-silicon design through post-silicon debug to production qualification.
  • •Collaborate with chip architects, design engineers, and verification teams to define, optimize, and standardize DFT strategies across projects.
  • •Supervise implementation of ATPG, scan compression, memory BIST, and other advanced DFT techniques to improve coverage and efficiency.
  • •Guide silicon failure debugging and root-cause analysis to improve yield and reliability.

Key Requirements

  • •BTech/MTech in Electrical/Computer Engineering or a related field with 10+ years of demonstrated experience.
  • •Hands-on experience with DFT features such as scan insertion, BIST, or boundary scan.
  • •Experience leading and developing engineering teams, including mentoring, performance management, and project planning.
  • •Proficiency across the full product lifecycle from pre-silicon design to silicon bring-up and production qualification.
Experience:10-14 yearsASICSemiconductorsNetworking5G
Education:Master's in Electrical/Computer Engineering
Skills:MentorshipCommunicationProject planningRoot-cause analysisStakeholder management
Tech Stack:DFTATPGScan insertionScan compressionBISTBoundary scanMemory BISTSilicon debugProduction qualification

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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Glassdoor: 4.0
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